From 73cdc66de5c545775547a94d8ec0efbc0fdfb38a Mon Sep 17 00:00:00 2001 From: NeoZng Date: Thu, 2 Feb 2023 15:21:22 +0800 Subject: [PATCH] =?UTF-8?q?=E6=9B=B4=E6=96=B0=E4=BA=86CUBEMX=E9=85=8D?= =?UTF-8?q?=E7=BD=AE,=E6=B7=BB=E5=8A=A0=E4=BA=86=E6=89=80=E6=9C=89?= =?UTF-8?q?=E5=BC=95=E8=84=9A=E5=92=8C=E5=A4=96=E9=83=A8=E4=B8=AD=E6=96=AD?= =?UTF-8?q?.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .mxproject | 8 +- .../Inc/stm32f4xx_hal_crc.h | 181 ++ .../Inc/stm32f4xx_hal_dac.h | 480 ++++++ .../Inc/stm32f4xx_hal_dac_ex.h | 205 +++ .../Inc/stm32f4xx_hal_gpio.h | 464 +++--- .../Inc/stm32f4xx_ll_crc.h | 201 +++ .../Inc/stm32f4xx_ll_dac.h | 1455 +++++++++++++++++ .../Src/stm32f4xx_hal_crc.c | 328 ++++ .../Src/stm32f4xx_hal_dac.c | 1341 +++++++++++++++ .../Src/stm32f4xx_hal_dac_ex.c | 495 ++++++ HAL_N_Middlewares/Inc/FreeRTOSConfig.h | 2 +- HAL_N_Middlewares/Inc/adc.h | 2 +- HAL_N_Middlewares/Inc/can.h | 2 +- HAL_N_Middlewares/Inc/crc.h | 52 + HAL_N_Middlewares/Inc/dac.h | 52 + HAL_N_Middlewares/Inc/dma.h | 2 +- HAL_N_Middlewares/Inc/gpio.h | 2 +- HAL_N_Middlewares/Inc/i2c.h | 2 +- HAL_N_Middlewares/Inc/main.h | 12 +- HAL_N_Middlewares/Inc/rng.h | 2 +- HAL_N_Middlewares/Inc/rtc.h | 2 +- HAL_N_Middlewares/Inc/spi.h | 2 +- HAL_N_Middlewares/Inc/stm32f4xx_hal_conf.h | 4 +- HAL_N_Middlewares/Inc/stm32f4xx_it.h | 19 +- HAL_N_Middlewares/Inc/tim.h | 2 +- HAL_N_Middlewares/Inc/usart.h | 2 +- HAL_N_Middlewares/Inc/usb_device.h | 2 +- HAL_N_Middlewares/Inc/usbd_cdc_if.h | 2 +- HAL_N_Middlewares/Inc/usbd_conf.h | 2 +- HAL_N_Middlewares/Inc/usbd_desc.h | 2 +- HAL_N_Middlewares/Src/adc.c | 26 +- HAL_N_Middlewares/Src/can.c | 2 +- HAL_N_Middlewares/Src/crc.c | 85 + HAL_N_Middlewares/Src/dac.c | 116 ++ HAL_N_Middlewares/Src/dma.c | 31 +- HAL_N_Middlewares/Src/gpio.c | 21 +- HAL_N_Middlewares/Src/i2c.c | 63 +- HAL_N_Middlewares/Src/rng.c | 2 +- HAL_N_Middlewares/Src/rtc.c | 2 +- HAL_N_Middlewares/Src/spi.c | 107 +- HAL_N_Middlewares/Src/stm32f4xx_hal_msp.c | 2 +- HAL_N_Middlewares/Src/stm32f4xx_it.c | 241 ++- HAL_N_Middlewares/Src/tim.c | 11 +- HAL_N_Middlewares/Src/usart.c | 8 +- HAL_N_Middlewares/Src/usb_device.c | 2 +- HAL_N_Middlewares/Src/usbd_cdc_if.c | 2 +- HAL_N_Middlewares/Src/usbd_conf.c | 2 +- HAL_N_Middlewares/Src/usbd_desc.c | 2 +- Makefile | 4 +- assets/00937839b59a4c039ee8ecb8a5136e3c.png | Bin 0 -> 139181 bytes assets/image-20230202151939109.png | Bin 0 -> 32208 bytes bsp/gpio/bsp_gpio.c | 22 +- bsp/gpio/bsp_gpio.h | 81 +- bsp/gpio/bsp_gpio.md | 3 + modules/ist8310/ist8310.h | 2 +- modules/referee/{crc.c => crc_ref.c} | 2 +- modules/referee/{crc.h => crc_ref.h} | 0 57 files changed, 5843 insertions(+), 323 deletions(-) create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c create mode 100644 HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c create mode 100644 HAL_N_Middlewares/Inc/crc.h create mode 100644 HAL_N_Middlewares/Inc/dac.h create mode 100644 HAL_N_Middlewares/Src/crc.c create mode 100644 HAL_N_Middlewares/Src/dac.c create mode 100644 assets/00937839b59a4c039ee8ecb8a5136e3c.png create mode 100644 assets/image-20230202151939109.png rename modules/referee/{crc.c => crc_ref.c} (99%) rename modules/referee/{crc.h => crc_ref.h} (100%) diff --git a/.mxproject b/.mxproject index a03dc7e..0477ad5 100644 --- a/.mxproject +++ b/.mxproject @@ -1,16 +1,16 @@ [PreviousLibFiles] -LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pcd.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pcd_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usb.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_adc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_adc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_i2c.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_i2c_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rng.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rng.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rtc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rtc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_spi.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_tim_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_tim.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Middlewares\Third_Party\FreeRTOS\Source\include\croutine.h;Middlewares\Third_Party\FreeRTOS\Source\include\deprecated_definitions.h;Middlewares\Third_Party\FreeRTOS\Source\include\event_groups.h;Middlewares\Third_Party\FreeRTOS\Source\include\FreeRTOS.h;Middlewares\Third_Party\FreeRTOS\Source\include\list.h;Middlewares\Third_Party\FreeRTOS\Source\include\message_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_prototypes.h;Middlewares\Third_Party\FreeRTOS\Source\include\mpu_wrappers.h;Middlewares\Third_Party\FreeRTOS\Source\include\portable.h;Middlewares\Third_Party\FreeRTOS\Source\include\projdefs.h;Middlewares\Third_Party\FreeRTOS\Source\include\queue.h;Middlewares\Third_Party\FreeRTOS\Source\include\semphr.h;Middlewares\Third_Party\FreeRTOS\Source\include\stack_macros.h;Middlewares\Third_Party\FreeRTOS\Source\include\StackMacros.h;Middlewares\Third_Party\FreeRTOS\Source\include\stream_buffer.h;Middlewares\Third_Party\FreeRTOS\Source\include\task.h;Middlewares\Third_Party\FreeRTOS\Source\include\timers.h;Middlewares\Third_Party\FreeRTOS\Source\include\atomic.h;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS\cmsis_os.h;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\portmacro.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_core.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_ctlreq.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_def.h;Middlewares\ST\STM32_USB_Device_Library\Core\Inc\usbd_ioreq.h;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc\usbd_cdc.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pcd_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_usb.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\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[PreviousUsedMakefileFiles] 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HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Middlewares\Third_Party\FreeRTOS\Source\include;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;Middlewares\ST\STM32_USB_Device_Library\Core\Inc;Middlewares\ST\STM32_USB_Device_Library\Class\CDC\Inc;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Middlewares\ST\ARM\DSP\Inc;Inc; CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] HeaderPath=..\Inc -HeaderFiles=gpio.h;FreeRTOSConfig.h;adc.h;can.h;dma.h;i2c.h;rng.h;rtc.h;spi.h;tim.h;usart.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; +HeaderFiles=gpio.h;FreeRTOSConfig.h;adc.h;can.h;crc.h;dac.h;dma.h;i2c.h;rng.h;rtc.h;spi.h;tim.h;usart.h;usb_device.h;usbd_conf.h;usbd_desc.h;usbd_cdc_if.h;stm32f4xx_it.h;stm32f4xx_hal_conf.h;main.h; SourcePath=..\Src -SourceFiles=gpio.c;freertos.c;adc.c;can.c;dma.c;i2c.c;rng.c;rtc.c;spi.c;tim.c;usart.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; +SourceFiles=gpio.c;freertos.c;adc.c;can.c;crc.c;dac.c;dma.c;i2c.c;rng.c;rtc.c;spi.c;tim.c;usart.c;usb_device.c;usbd_conf.c;usbd_desc.c;usbd_cdc_if.c;stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c; [ThirdPartyIp] ThirdPartyIpNumber=1 diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h new file mode 100644 index 0000000..41edbe3 --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_crc.h @@ -0,0 +1,181 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_crc.h + * @author MCD Application Team + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_CRC_H +#define STM32F4xx_HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ + +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; + + +/** + * @brief CRC Handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + HAL_LockTypeDef Lock; /*!< CRC Locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + +} CRC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state. + * @param __HANDLE__ CRC handle. + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Reset CRC Data Register. + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) + +/** + * @brief Store data in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) + +/** + * @brief Return the data stored in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_CRC_H */ diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h new file mode 100644 index 0000000..a79ca73 --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac.h @@ -0,0 +1,480 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dac.h + * @author MCD Application Team + * @brief Header file of DAC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_DAC_H +#define STM32F4xx_HAL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +#if defined(DAC) + +/** @addtogroup DAC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Types DAC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ + HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ + HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ + HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ + HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ + +} HAL_DAC_StateTypeDef; + +/** + * @brief DAC handle Structure definition + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +typedef struct __DAC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +{ + DAC_TypeDef *Instance; /*!< Register base address */ + + __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ + + HAL_LockTypeDef Lock; /*!< DAC locking object */ + + DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ + + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ + + __IO uint32_t ErrorCode; /*!< DAC Error code */ + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); +#if defined(DAC_CHANNEL2_SUPPORT) + void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); +#endif /* DAC_CHANNEL2_SUPPORT */ + + void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +} DAC_HandleTypeDef; + +/** + * @brief DAC Configuration regular Channel structure definition + */ +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ + +} DAC_ChannelConfTypeDef; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL DAC Callback ID enumeration definition + */ +typedef enum +{ + HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ + HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ + HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ + HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ +#if defined(DAC_CHANNEL2_SUPPORT) + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ + HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ + HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ + HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ +#endif /* DAC_CHANNEL2_SUPPORT */ + HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ + HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ + HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ +} HAL_DAC_CallbackIDTypeDef; + +/** + * @brief HAL DAC Callback pointer definition + */ +typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_Error_Code DAC Error Code + * @{ + */ +#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ +#endif /* DAC_CHANNEL2_SUPPORT */ +#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ +#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup DAC_trigger_selection DAC trigger selection + * @{ + */ +#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ + +/** + * @} + */ + +/** @defgroup DAC_output_buffer DAC output buffer + * @{ + */ +#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U +#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1) + +/** + * @} + */ + +/** @defgroup DAC_Channel_selection DAC Channel selection + * @{ + */ +#define DAC_CHANNEL_1 0x00000000U +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_CHANNEL_2 0x00000010U +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ + +/** @defgroup DAC_data_alignment DAC data alignment + * @{ + */ +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U + +/** + * @} + */ + +/** @defgroup DAC_flags_definition DAC flags definition + * @{ + */ +#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ + +/** @defgroup DAC_IT_definition DAC IT definition + * @{ + */ +#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @brief Reset DAC handle state. + * @param __HANDLE__ specifies the DAC handle. + * @retval None + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** @brief Enable the DAC channel. + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel + * @retval None + */ +#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ + ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + +/** @brief Disable the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. + * @retval None + */ +#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ + ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + +/** @brief Set DHR12R1 alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) + +#if defined(DAC_CHANNEL2_SUPPORT) +/** @brief Set DHR12R2 alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** @brief Set DHR12RD alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) + +/** @brief Enable the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt + * @retval None + */ +#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) + +/** @brief Disable the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt + * @retval None + */ +#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) + +/** @brief Check whether the specified DAC interrupt source is enabled or not. + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt + * @retval State of interruption (SET or RESET) + */ +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Get the selected DAC's flag status. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to get. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag + * @retval None + */ +#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the DAC's flag. + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to clear. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag + * @retval None + */ +#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) + +#if defined(DAC_CHANNEL2_SUPPORT) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) +#else +#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) +#endif /* DAC_CHANNEL2_SUPPORT */ + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) + +/** + * @} + */ + +/* Include DAC HAL Extended module */ +#include "stm32f4xx_hal_dac_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); + +void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/* DAC callback registering/unregistering */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions DAC Private Functions + * @{ + */ +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F4xx_HAL_DAC_H */ + diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h new file mode 100644 index 0000000..db10990 --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dac_ex.h @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dac_ex.h + * @author MCD Application Team + * @brief Header file of DAC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_HAL_DAC_EX_H +#define STM32F4xx_HAL_DAC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +#if defined(DAC) + +/** @addtogroup DACEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL State structures definition + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Constants DACEx Exported Constants + * @{ + */ + +/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude + * @{ + */ +#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup DACEx_Private_Macros DACEx Private Macros + * @{ + */ +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/* Extended features functions ***********************************************/ + +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ + +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); + +#if defined(DAC_CHANNEL2_SUPPORT) +#endif +HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); + +#if defined(DAC_CHANNEL2_SUPPORT) +#endif +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DACEx_Private_Functions + * @{ + */ +#if defined(DAC_CHANNEL2_SUPPORT) +/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */ +/* are called by HAL_DAC_Start_DMA */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_HAL_DAC_EX_H */ + diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h index 77a8d95..5f3d749 100644 --- a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h @@ -1,325 +1,325 @@ /** - ****************************************************************************** - * @file stm32f4xx_hal_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file stm32f4xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HAL_GPIO_H #define __STM32F4xx_HAL_GPIO_H #ifdef __cplusplus -extern "C" -{ + extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" - /** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ - /** @addtogroup GPIO - * @{ - */ +/** @addtogroup GPIO + * @{ + */ - /* Exported types ------------------------------------------------------------*/ - /** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ - /** - * @brief GPIO Init structure definition - */ - typedef struct - { - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode_define */ + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull_define */ + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed_define */ + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_Alternate_function_selection */ - } GPIO_InitTypeDef; + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +}GPIO_InitTypeDef; - /** - * @brief GPIO Bit SET and Bit RESET enumeration - */ - typedef enum - { - GPIO_PIN_RESET = 0, - GPIO_PIN_SET - } GPIO_PinState; +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +}GPIO_PinState; /** - * @} - */ + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ + * @{ + */ /** @defgroup GPIO_pins_define GPIO pins define - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ -#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ +#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ /** - * @} - */ + * @} + */ /** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode - * Elements values convention: 0x00WX00YZ - * - W : EXTI trigger detection on 3 bits - * - X : EXTI mode (IT or Event) on 2 bits - * - Y : Output type (Push Pull or Open Drain) on 1 bit - * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits - * @{ - */ -#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** - * @} - */ + * @} + */ /** @defgroup GPIO_speed_define GPIO speed define - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ - /** - * @} - */ + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ +#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ +/** + * @} + */ - /** @defgroup GPIO_pull_define GPIO pull define + /** @defgroup GPIO_pull_define GPIO pull define * @brief GPIO Pull-Up or Pull-Down Activation * @{ - */ -#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ -#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ + */ +#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ /** - * @} - */ - + * @} + */ + /** - * @} - */ + * @} + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ + * @{ + */ /** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__ specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** - * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** - * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__ specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) /** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) /** - * @} - */ + * @} + */ /* Include GPIO HAL Extension module */ #include "stm32f4xx_hal_gpio_ex.h" - /* Exported functions --------------------------------------------------------*/ - /** @addtogroup GPIO_Exported_Functions - * @{ - */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ - /** @addtogroup GPIO_Exported_Functions_Group1 - * @{ - */ - /* Initialization and de-initialization functions *****************************/ - void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); - void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); - /** - * @} - */ +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ - /** @addtogroup GPIO_Exported_Functions_Group2 - * @{ - */ - /* IO operation functions *****************************************************/ - GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); - void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); - void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); - HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); - void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); - void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** - * @} - */ + * @} + */ /** - * @} - */ + * @} + */ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ -#define GPIO_MODE_Pos 0U -#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) -#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) -#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) -#define MODE_AF (0x2UL << GPIO_MODE_Pos) -#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) -#define OUTPUT_TYPE_Pos 4U -#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) -#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) -#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) -#define EXTI_MODE_Pos 16U -#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) -#define EXTI_IT (0x1UL << EXTI_MODE_Pos) -#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) -#define TRIGGER_MODE_Pos 20U -#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) -#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) -#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) + * @{ + */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) /** - * @} - */ + * @} + */ /* Private macros ------------------------------------------------------------*/ /** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ + * @{ + */ #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) || \ - ((MODE) == GPIO_MODE_OUTPUT_PP) || \ - ((MODE) == GPIO_MODE_OUTPUT_OD) || \ - ((MODE) == GPIO_MODE_AF_PP) || \ - ((MODE) == GPIO_MODE_AF_OD) || \ - ((MODE) == GPIO_MODE_IT_RISING) || \ - ((MODE) == GPIO_MODE_IT_FALLING) || \ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) || \ - ((MODE) == GPIO_MODE_EVT_RISING) || \ - ((MODE) == GPIO_MODE_EVT_FALLING) || \ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || \ +#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ ((MODE) == GPIO_MODE_ANALOG)) -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ - ((SPEED_LOOP) == GPIO_SPEED_FREQ_HIGH) || ((SPEED_LOOP) == GPIO_SPEED_FREQ_VERY_HIGH)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ ((PULL) == GPIO_PULLDOWN)) - /** - * @} - */ +/** + * @} + */ - /* Private functions ---------------------------------------------------------*/ - /** @defgroup GPIO_Private_Functions GPIO Private Functions - * @{ - */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ - /** - * @} - */ +/** + * @} + */ - /** - * @} - */ +/** + * @} + */ - /** - * @} - */ +/** + * @} + */ #ifdef __cplusplus } #endif #endif /* __STM32F4xx_HAL_GPIO_H */ + diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h new file mode 100644 index 0000000..0a28006 --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_crc.h @@ -0,0 +1,201 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_crc.h + * @author MCD Application Team + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_CRC_H +#define STM32F4xx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_LL_CRC_H */ diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h new file mode 100644 index 0000000..ea1500b --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dac.h @@ -0,0 +1,1455 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_dac.h + * @author MCD Application Team + * @brief Header file of DAC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F4xx_LL_DAC_H +#define STM32F4xx_LL_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined(DAC) + +/** @defgroup DAC_LL DAC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Constants DAC Private Constants + * @{ + */ + +/* Internal masks for DAC channels definition */ +/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ +/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ +/* - channel bits position into register SWTRIG */ +/* - channel register offset of data holding register DHRx */ +/* - channel register offset of data output register DORx */ +#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) +#else +#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET) +#endif /* DAC_CHANNEL2_SUPPORT */ + +#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) +#else +#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) +#endif /* DAC_CHANNEL2_SUPPORT */ + +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ +#endif /* DAC_CHANNEL2_SUPPORT */ +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ + | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) + +#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus + DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) +#endif /* DAC_CHANNEL2_SUPPORT */ + + +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, + DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted + to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted + to position 0 */ + +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 16 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx + channel 1 or 2 versus DORx channel 1 + (shifted left of 28 bits) */ + +/* DAC registers bits positions */ +#if defined(DAC_CHANNEL2_SUPPORT) +#endif +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos + +/* Miscellaneous data */ +#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 + bits (voltage range determined by analog voltage + references Vref+ and Vref-, refer to reference manual) */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Private_Macros DAC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of DAC instance. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: + internal (SW start) or from external peripheral + (timer event, external interrupt line). + This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetTriggerSource(). */ + + uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveAutoGeneration(). */ + + uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. + If waveform automatic generation mode is set to noise, this parameter + can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, + this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + @note If waveform automatic generation mode is disabled, + this parameter is discarded. + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveNoiseLFSR(), + @ref LL_DAC_SetWaveTriangleAmplitude() + depending on the wave automatic generation selected. */ + + uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. + This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputBuffer(). */ +} LL_DAC_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_LL_EC_GET_FLAG DAC flags + * @brief Flags defines which can be used with LL_DAC_ReadReg function + * @{ + */ +/* DAC channel 1 flags */ +#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ +#if defined(DAC_CHANNEL2_SUPPORT) +/* DAC channel 2 flags */ +#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_IT DAC interruptions + * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions + * @{ + */ +#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_CHANNEL DAC channels + * @{ + */ +#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ +#endif /* DAC_CHANNEL2_SUPPORT */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source + * @{ + */ +#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode + * @{ + */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits + * @{ + */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude + * @{ + */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer + * @{ + */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution + * @{ + */ +#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose + * @{ + */ +/* List of DAC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ +/** + * @} + */ + +/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays + * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Delay for DAC channel voltage settling time from DAC channel startup */ +/* (transition from disable to enable). */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm (min), 50pF (max) */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tWAKEUP"). */ +/* Unit: us */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ + +/* Delay for DAC channel voltage settling time. */ +/* Note: DAC channel startup time depends on board application environment: */ +/* impedance connected to DAC channel output. */ +/* The delay below is specified under conditions: */ +/* - voltage maximum transition (lowest to highest value) */ +/* - until voltage reaches final value +-1LSB */ +/* - DAC channel output buffer enabled */ +/* - load impedance of 5kOhm min, 50pF max */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSETTLING"). */ +/* Unit: us */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros + * @{ + */ + +/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros + * @{ + */ + +/** + * @brief Write a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DAC register + * @param __INSTANCE__ DAC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) + +/** + * @} + */ + +/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro + * @{ + */ + +/** + * @brief Helper macro to get DAC channel number in decimal format + * from literals LL_DAC_CHANNEL_x. + * Example: + * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) + * will return decimal number "1". + * @note The input can be a value from functions where a channel + * number is returned. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval 1...2 (value "2" depending on DAC channel 2 availability) + */ +#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((__CHANNEL__) & DAC_SWTR_CHX_MASK) + +/** + * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x + * from number in decimal format. + * Example: + * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) + * will return a data equivalent to "LL_DAC_CHANNEL_1". + * @note If the input parameter does not correspond to a DAC channel, + * this macro returns value '0'. + * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + */ +#if defined(DAC_CHANNEL2_SUPPORT) +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1UL) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + (((__DECIMAL_NB__) == 2UL) \ + ? ( \ + LL_DAC_CHANNEL_2 \ + ) \ + : \ + ( \ + 0UL \ + ) \ + ) \ + ) +#else +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1UL) \ + ? ( \ + LL_DAC_CHANNEL_1 \ + ) \ + : \ + ( \ + 0UL \ + ) \ + ) +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Helper macro to define the DAC conversion data full-scale digital + * value corresponding to the selected DAC resolution. + * @note DAC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) + +/** + * @brief Helper macro to calculate the DAC conversion data (unit: digital + * value) corresponding to a voltage (unit: mVolt). + * @note This helper macro is intended to provide input data in voltage + * rather than digital value, + * to be used with LL DAC functions such as + * @ref LL_DAC_ConvertData12RightAligned(). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel + * (unit: mVolt). + * @param __DAC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_DAC_RESOLUTION_12B + * @arg @ref LL_DAC_RESOLUTION_8B + * @retval DAC conversion data (unit: digital value) + */ +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ + __DAC_VOLTAGE__,\ + __DAC_RESOLUTION__) \ +((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ +) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions + * @{ + */ +/** + * @brief Set the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note To set conversion trigger source, DAC channel must be disabled. + * Otherwise, the setting is discarded. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n + * CR TSEL2 LL_DAC_SetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) +{ + MODIFY_REG(DACx->CR, + DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the conversion trigger source for the selected DAC channel. + * @note For conversion trigger source to be effective, DAC trigger + * must be enabled using function @ref LL_DAC_EnableTrigger(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n + * CR TSEL2 LL_DAC_GetTriggerSource + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIG_SOFTWARE + * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 + */ +__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_SetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param WaveAutoGeneration This parameter can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) +{ + MODIFY_REG(DACx->CR, + DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the waveform automatic generation mode + * for the selected DAC channel. + * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n + * CR WAVE2 LL_DAC_GetWaveAutoGeneration + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE + * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_SetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param NoiseLFSRMask This parameter can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the noise waveform generation for the selected DAC channel: + * Noise mode and parameters LFSR (linear feedback shift register). + * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n + * CR MAMP2 LL_DAC_GetWaveNoiseLFSR + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 + * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @note For wave generation to be effective, DAC channel + * wave generation mode must be enabled using + * function @ref LL_DAC_SetWaveAutoGeneration(). + * @note This setting can be set when the selected DAC channel is disabled + * (otherwise, the setting operation is ignored). + * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param TriangleAmplitude This parameter can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, + uint32_t TriangleAmplitude) +{ + MODIFY_REG(DACx->CR, + DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the triangle waveform generation for the selected DAC channel: + * triangle mode and amplitude. + * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n + * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 + * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 + */ +__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @brief Set the output buffer for the selected DAC channel. + * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n + * CR BOFF2 LL_DAC_SetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param OutputBuffer This parameter can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + * @retval None + */ +__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) +{ + MODIFY_REG(DACx->CR, + DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), + OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get the output buffer state for the selected DAC channel. + * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n + * CR BOFF2 LL_DAC_GetOutputBuffer + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE + * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE + */ +__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n + * CR DMAEN2 LL_DAC_EnableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC DMA transfer request of the selected channel. + * @note To configure DMA source address (peripheral address), + * use function @ref LL_DAC_DMA_GetRegAddr(). + * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n + * CR DMAEN2 LL_DAC_DisableDMAReq + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC DMA transfer request state of the selected channel. + * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) + * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n + * CR DMAEN2 LL_DAC_IsDMAReqEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return ((READ_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +} + +/** + * @brief Function to help to configure DMA transfer to DAC: retrieve the + * DAC register address from DAC instance and a list of DAC registers + * intended to be used (most commonly) with DMA transfer. + * @note These DAC registers are data holding registers: + * when DAC conversion is requested, DAC generates a DMA transfer + * request to have data available in DAC data holding registers. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * (uint32_t)&< array or variable >, + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, + * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); + * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n + * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n + * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Register This parameter can be one of the following values: + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED + * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED + * @retval DAC register address + */ +__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) +{ + /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ + /* DAC channel selected. */ + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); +} +/** + * @} + */ + +/** @defgroup DAC_LL_EF_Operation Operation on DAC channels + * @{ + */ + +/** + * @brief Enable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Enable\n + * CR EN2 LL_DAC_Enable + * @note After enable from off state, DAC channel requires a delay + * for output voltage to reach accuracy +/- 1 LSB. + * Refer to device datasheet, parameter "tWAKEUP". + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC selected channel. + * @rmtoll CR EN1 LL_DAC_Disable\n + * CR EN2 LL_DAC_Disable + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC enable state of the selected channel. + * (0: DAC channel is disabled, 1: DAC channel is enabled) + * @rmtoll CR EN1 LL_DAC_IsEnabled\n + * CR EN2 LL_DAC_IsEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return ((READ_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +} + +/** + * @brief Enable DAC trigger of the selected channel. + * @note - If DAC trigger is disabled, DAC conversion is performed + * automatically once the data holding register is updated, + * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ... + * - If DAC trigger is enabled, DAC conversion is performed + * only when a hardware of software trigger event is occurring. + * Select trigger source using + * function @ref LL_DAC_SetTriggerSource(). + * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n + * CR TEN2 LL_DAC_EnableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Disable DAC trigger of the selected channel. + * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n + * CR TEN2 LL_DAC_DisableTrigger + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + CLEAR_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); +} + +/** + * @brief Get DAC trigger state of the selected channel. + * (0: DAC trigger is disabled, 1: DAC trigger is enabled) + * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n + * CR TEN2 LL_DAC_IsTriggerEnabled + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + return ((READ_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); +} + +/** + * @brief Trig DAC conversion by software for the selected DAC channel. + * @note Preliminarily, DAC trigger must be set to software trigger + * using function + * @ref LL_DAC_Init() + * @ref LL_DAC_SetTriggerSource() + * with parameter "LL_DAC_TRIGGER_SOFTWARE". + * and DAC trigger must be enabled using + * function @ref LL_DAC_EnableTrigger(). + * @note For devices featuring DAC with 2 channels: this function + * can perform a SW start of both DAC channels simultaneously. + * Two channels can be selected as parameter. + * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) + * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n + * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion + * @param DACx DAC instance + * @param DAC_Channel This parameter can a combination of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval None + */ +__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + SET_BIT(DACx->SWTRIGR, + (DAC_Channel & DAC_SWTR_CHX_MASK)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n + * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for the selected DAC channel. + * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n + * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for the selected DAC channel. + * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n + * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) +{ + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n + * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR12RD, + (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), + ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 12 bits left alignment (MSB aligned on bit 15), + * for both DAC channels. + * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n + * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF + * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) +{ + /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ + /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ + /* the 4 LSB must be taken into account for the shift value. */ + MODIFY_REG(DACx->DHR12LD, + (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), + ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); +} + +/** + * @brief Set the data to be loaded in the data holding register + * in format 8 bits left alignment (LSB aligned on bit 0), + * for both DAC channels. + * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n + * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned + * @param DACx DAC instance + * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF + * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) +{ + MODIFY_REG(DACx->DHR8RD, + (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), + ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Retrieve output data currently generated for the selected DAC channel. + * @note Whatever alignment and resolution settings + * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": + * @ref LL_DAC_ConvertData12RightAligned(), ...), + * output data format is 12 bits right aligned (LSB aligned on bit 0). + * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n + * DOR2 DACC2DOR LL_DAC_RetrieveOutputData + * @param DACx DAC instance + * @param DAC_Channel This parameter can be one of the following values: + * @arg @ref LL_DAC_CHANNEL_1 + * @arg @ref LL_DAC_CHANNEL_2 (1) + * + * (1) On this STM32 serie, parameter not available on all devices. + * Refer to device datasheet for channels availability. + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) +{ + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + + return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); +} + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Get DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Get DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Clear DAC underrun flag for DAC channel 1 + * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Clear DAC underrun flag for DAC channel 2 + * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) +{ + WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ + +/** @defgroup DAC_LL_EF_IT_Management IT management + * @{ + */ + +/** + * @brief Enable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Enable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Disable DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Disable DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 + * @param DACx DAC instance + * @retval None + */ +__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) +{ + CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Get DMA underrun interrupt for DAC channel 1 + * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Get DMA underrun interrupt for DAC channel 2 + * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 + * @param DACx DAC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) +{ + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F4xx_LL_DAC_H */ + diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c new file mode 100644 index 0000000..2e86b2b --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_crc.c + * @author MCD Application Team + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) + (++) specify input data format + (++) specify input or output data inversion mode if any + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if (hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) compute the 32-bit CRC value of a 32-bit data buffer + using combination of the previous CRC value and the new one. + + [..] or + + (+) compute the 32-bit CRC value of a 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 32-bit CRC value of a 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer. + * @param BufferLength input data buffer length (number of uint32_t words). + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Enter Data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @brief Compute the 32-bit CRC value of a 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer. + * @param BufferLength input data buffer length (number of uint32_t words). + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + /* Enter 32-bit input data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRC handle state. + * @param hcrc CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +{ + /* Return CRC handle state */ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c new file mode 100644 index 0000000..9023e3e --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c @@ -0,0 +1,1341 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dac.c + * @author MCD Application Team + * @brief DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Digital to Analog Converter (DAC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### DAC Peripheral features ##### + ============================================================================== + [..] + *** DAC Channels *** + ==================== + [..] + STM32F4 devices integrate two 12-bit Digital Analog Converters + + The 2 converters (i.e. channel1 & channel2) + can be used independently or simultaneously (dual mode): + (#) DAC channel1 with DAC_OUT1 (PA4) as output + (#) DAC channel2 with DAC_OUT2 (PA5) as output + + *** DAC Triggers *** + ==================== + [..] + Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] + Digital to Analog conversion can be triggered by: + (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. + The used pin (GPIOx_PIN_9) must be configured in input mode. + + (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 + (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...) + + (#) Software using DAC_TRIGGER_SOFTWARE + + *** DAC Buffer mode feature *** + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to + reduce the output impedance, and to drive external loads directly + without having to add an external operational amplifier. + To enable, the output buffer use + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + [..] + (@) Refer to the device datasheet for more details about output + impedance value with and without output buffer. + + *** DAC wave generation feature *** + =================================== + [..] + Both DAC channels can be used to generate + (#) Noise wave + (#) Triangle wave + + *** DAC data format *** + ======================= + [..] + The DAC data format can be: + (#) 8-bit right alignment using DAC_ALIGN_8B_R + (#) 12-bit left alignment using DAC_ALIGN_12B_L + (#) 12-bit right alignment using DAC_ALIGN_12B_R + + *** DAC data value to voltage correspondence *** + ================================================ + [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + [..] + DAC_OUTx = VREF+ * DOR / 4095 + (+) with DOR is the Data Output Register + [..] + VREF+ is the input voltage reference (refer to the device datasheet) + [..] + e.g. To set DAC_OUT1 to 0.7V, use + (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA request can be generated when an external trigger (but not a software trigger) + occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). + DMA1 requests are mapped as following: + (#) DAC channel1 mapped on DMA1 Stream5 channel7 which must be + already configured + (#) DAC channel2 mapped on DMA1 Stream6 channel7 which must be + already configured + + [..] + (@) For Dual mode and specific signal (Triangle and noise) generation please + refer to Extended Features Driver description + + ##### How to use this driver ##### + ============================================================================== + [..] + (+) DAC APB clock must be enabled to get write access to DAC + registers using HAL_DAC_Init() + (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. + (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. + (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. + + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() + (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. + (+) Stop the DAC peripheral using HAL_DAC_Stop() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() + (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_DAC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. + (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. + (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. + (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. + (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. + (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. + (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. + (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. + (+) MspInitCallback : DAC MspInit. + (+) MspDeInitCallback : DAC MspdeInit. + (+) All Callbacks + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit + or HAL_DAC_Init function. + + When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** DAC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DAC HAL driver. + + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral + (+) __HAL_DAC_DISABLE : Disable the DAC peripheral + (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags + (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status + + [..] + (@) You can refer to the DAC HAL driver header file for more useful macros + +@endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED +#if defined(DAC) + +/** @defgroup DAC DAC + * @brief DAC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions -------------------------------------------------------*/ + +/** @defgroup DAC_Exported_Functions DAC Exported Functions + * @{ + */ + +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DAC peripheral according to the specified parameters + * in the DAC_InitStruct and initialize the associated handle. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) +{ + /* Check DAC handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + if (hdac->State == HAL_DAC_STATE_RESET) + { +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the DAC Callback settings */ + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; +#if defined(DAC_CHANNEL2_SUPPORT) + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; +#endif /* DAC_CHANNEL2_SUPPORT */ + if (hdac->MspInitCallback == NULL) + { + hdac->MspInitCallback = HAL_DAC_MspInit; + } +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + /* Allocate lock resource and initialize it */ + hdac->Lock = HAL_UNLOCKED; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + /* Init the low level hardware */ + hdac->MspInitCallback(hdac); +#else + /* Init the low level hardware */ + HAL_DAC_MspInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Initialize the DAC state*/ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) +{ + /* Check DAC handle */ + if (hdac == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + if (hdac->MspDeInitCallback == NULL) + { + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + } + /* DeInit the low level hardware */ + hdac->MspDeInitCallback(hdac); +#else + /* DeInit the low level hardware */ + HAL_DAC_MspDeInit(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + /* Set DAC error code to none */ + hdac->ErrorCode = HAL_DAC_ERROR_NONE; + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the DAC MSP. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the DAC MSP. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + +@endverbatim + * @{ + */ + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + + if (Channel == DAC_CHANNEL_1) + { + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + } +#if defined(DAC_CHANNEL2_SUPPORT) + else + { + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) + { + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); + } + } +#endif /* DAC_CHANNEL2_SUPPORT */ + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpreg = 0U; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + if (Channel == DAC_CHANNEL_1) + { + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Case of use of channel 1 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + } +#if defined(DAC_CHANNEL2_SUPPORT) + else + { + /* Set the DMA transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; + + /* Set the DMA half transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; + + /* Set the DMA error callback for channel2 */ + hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; + + /* Enable the selected DAC channel2 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Case of use of channel 2 */ + switch (Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + } +#endif /* DAC_CHANNEL2_SUPPORT */ + + /* Enable the DMA Stream */ + if (Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } +#if defined(DAC_CHANNEL2_SUPPORT) + else + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + } +#endif /* DAC_CHANNEL2_SUPPORT */ + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + if (status == HAL_OK) + { + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); + } + else + { + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + } + + /* Return function status */ + return status; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA Stream */ + + /* Channel1 is used */ + if (Channel == DAC_CHANNEL_1) + { + /* Disable the DMA Stream */ + (void)HAL_DMA_Abort(hdac->DMA_Handle1); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); + } +#if defined(DAC_CHANNEL2_SUPPORT) + else /* Channel2 is used for */ + { + /* Disable the DMA Stream */ + (void)HAL_DMA_Abort(hdac->DMA_Handle2); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); + } +#endif /* DAC_CHANNEL2_SUPPORT */ + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles DAC interrupt request + * This function uses the interruption of DMA + * underrun. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) +{ + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) + { + /* Check underrun flag of DAC channel 1 */ + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel1 DMA underrun error */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh1(hdac); +#else + HAL_DAC_DMAUnderrunCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + } + +#if defined(DAC_CHANNEL2_SUPPORT) + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) + { + /* Check underrun flag of DAC channel 2 */ + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel2 DMA underrun error */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel2 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Error callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->DMAUnderrunCallbackCh2(hdac); +#else + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } + } +#endif /* DAC_CHANNEL2_SUPPORT */ +} + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0UL; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); + } +#if defined(DAC_CHANNEL2_SUPPORT) + else + { + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); + } +#endif /* DAC_CHANNEL2_SUPPORT */ + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Conversion complete callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel1. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel1. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels. + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + uint32_t result = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + if (Channel == DAC_CHANNEL_1) + { + result = hdac->Instance->DOR1; + } +#if defined(DAC_CHANNEL2_SUPPORT) + else + { + result = hdac->Instance->DOR2; + } +#endif /* DAC_CHANNEL2_SUPPORT */ + /* Returns the DAC channel data output register value */ + return result; +} + +/** + * @brief Configures the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Get the DAC CR value */ + tmpreg1 = hdac->Instance->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL)); + /* Configure for the selected DAC channel: buffer output, trigger */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); + /* Write to DAC CR */ + hdac->Instance->CR = tmpreg1; + /* Disable wave generation */ + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DAC state. + (+) Check the DAC Errors. + +@endverbatim + * @{ + */ + +/** + * @brief return the DAC handle state + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL state + */ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) +{ + /* Return DAC handle state */ + return hdac->State; +} + + +/** + * @brief Return the DAC error code + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval DAC Error Code + */ +uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) +{ + return hdac->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User DAC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID + * + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdac); + + if (hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = pCallback; + break; +#if defined(DAC_CHANNEL2_SUPPORT) + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = pCallback; + break; +#endif /* DAC_CHANNEL2_SUPPORT */ + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} + +/** + * @brief Unregister a User DAC Callback + * DAC Callback is redirected to the weak (surcharged) predefined callback + * @param hdac DAC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID + * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID + * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID + * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID + * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID + * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID + * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID + * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks + * @retval status + */ +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdac); + + if (hdac->State == HAL_DAC_STATE_READY) + { + switch (CallbackID) + { + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + break; +#if defined(DAC_CHANNEL2_SUPPORT) + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + break; +#endif /* DAC_CHANNEL2_SUPPORT */ + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + case HAL_DAC_ALL_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; +#if defined(DAC_CHANNEL2_SUPPORT) + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; +#endif /* DAC_CHANNEL2_SUPPORT */ + hdac->MspInitCallback = HAL_DAC_MspInit; + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hdac->State == HAL_DAC_STATE_RESET) + { + switch (CallbackID) + { + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdac); + return status; +} +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DAC_Private_Functions + * @{ + */ + +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh1(hdac); +#else + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh1(hdac); +#else + HAL_DAC_ErrorCallbackCh1(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c new file mode 100644 index 0000000..343dd98 --- /dev/null +++ b/HAL_N_Middlewares/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c @@ -0,0 +1,495 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_dac_ex.c + * @author MCD Application Team + * @brief Extended DAC HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the DAC peripheral. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + + *** Dual mode IO operation *** + ============================== + [..] + (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : + Use HAL_DACEx_DualGetValue() to get digital data to be converted and use + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in + Channel 1 and Channel 2. + + *** Signal generation operation *** + =================================== + [..] + (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. + (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. + + @endverbatim + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_DAC_MODULE_ENABLED + +#if defined(DAC) + +/** @defgroup DACEx DACEx + * @brief DAC Extended HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DACEx_Exported_Functions DACEx Exported Functions + * @{ + */ + +/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions + * @brief Extended IO operation functions + * +@verbatim + ============================================================================== + ##### Extended features functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion. + (+) Stop conversion. + (+) Start conversion and enable DMA transfer. + (+) Stop conversion and disable DMA transfer. + (+) Get result of conversion. + (+) Get result of dual mode conversion. + +@endverbatim + * @{ + */ + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Enables DAC and starts conversion of both channels. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) +{ + uint32_t tmp_swtrig = 0UL; + + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); + __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); + + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) + { + tmp_swtrig |= DAC_SWTRIGR_SWTRIG1; + } + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL))) + { + tmp_swtrig |= DAC_SWTRIGR_SWTRIG2; + } + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of both channels. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) +{ + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); + __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @brief Enable or disable the selected DAC channel wave generation. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Select max triangle amplitude. + * This parameter can be one of the following values: + * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 + * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 + * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 + * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 + * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 + * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 + * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 + * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 + * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 + * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 + * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the triangle wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable or disable the selected DAC channel wave generation. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: + * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the noise wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Set the specified data holding register value for dual DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_8B_R) + { + data = ((uint32_t)Data2 << 8U) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16U) | Data1; + } + + tmp = (uint32_t)hdac->Instance; + tmp += DAC_DHR12RD_ALIGNMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Conversion complete callback in non-blocking mode for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdac); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file + */ +} +#endif /* DAC_CHANNEL2_SUPPORT */ + + +/** + * @} + */ + +/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief Return the last data output value of the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +{ + uint32_t tmp = 0UL; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16UL; + + /* Returns the DAC channel data output register value */ + return tmp; +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DACEx_Private_Functions DACEx private functions + * @brief Extended private functions + * @{ + */ + +#if defined(DAC_CHANNEL2_SUPPORT) +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh2(hdac); +#else + HAL_DACEx_ErrorCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} +#endif /* DAC_CHANNEL2_SUPPORT */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + +#endif /* HAL_DAC_MODULE_ENABLED */ + +/** + * @} + */ + diff --git a/HAL_N_Middlewares/Inc/FreeRTOSConfig.h b/HAL_N_Middlewares/Inc/FreeRTOSConfig.h index 2881de6..a31f768 100644 --- a/HAL_N_Middlewares/Inc/FreeRTOSConfig.h +++ b/HAL_N_Middlewares/Inc/FreeRTOSConfig.h @@ -66,7 +66,7 @@ #define configMAX_PRIORITIES ( 7 ) #define configMINIMAL_STACK_SIZE ((uint16_t)128) #define configTOTAL_HEAP_SIZE ((size_t)15360) -#define configMAX_TASK_NAME_LEN ( 16 ) +#define configMAX_TASK_NAME_LEN ( 32 ) #define configUSE_16_BIT_TICKS 0 #define configUSE_MUTEXES 1 #define configQUEUE_REGISTRY_SIZE 8 diff --git a/HAL_N_Middlewares/Inc/adc.h b/HAL_N_Middlewares/Inc/adc.h index 218e684..830535e 100644 --- a/HAL_N_Middlewares/Inc/adc.h +++ b/HAL_N_Middlewares/Inc/adc.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/can.h b/HAL_N_Middlewares/Inc/can.h index 4dfe68c..f9d9695 100644 --- a/HAL_N_Middlewares/Inc/can.h +++ b/HAL_N_Middlewares/Inc/can.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/crc.h b/HAL_N_Middlewares/Inc/crc.h new file mode 100644 index 0000000..76ee893 --- /dev/null +++ b/HAL_N_Middlewares/Inc/crc.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file crc.h + * @brief This file contains all the function prototypes for + * the crc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern CRC_HandleTypeDef hcrc; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_CRC_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_H__ */ + diff --git a/HAL_N_Middlewares/Inc/dac.h b/HAL_N_Middlewares/Inc/dac.h new file mode 100644 index 0000000..9d07b27 --- /dev/null +++ b/HAL_N_Middlewares/Inc/dac.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dac.h + * @brief This file contains all the function prototypes for + * the dac.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern DAC_HandleTypeDef hdac; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DAC_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + diff --git a/HAL_N_Middlewares/Inc/dma.h b/HAL_N_Middlewares/Inc/dma.h index d343621..9b1e623 100644 --- a/HAL_N_Middlewares/Inc/dma.h +++ b/HAL_N_Middlewares/Inc/dma.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/gpio.h b/HAL_N_Middlewares/Inc/gpio.h index 45e27b1..6c03ac7 100644 --- a/HAL_N_Middlewares/Inc/gpio.h +++ b/HAL_N_Middlewares/Inc/gpio.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/i2c.h b/HAL_N_Middlewares/Inc/i2c.h index fae68df..102e57f 100644 --- a/HAL_N_Middlewares/Inc/i2c.h +++ b/HAL_N_Middlewares/Inc/i2c.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/main.h b/HAL_N_Middlewares/Inc/main.h index 554637b..1ceb2a8 100644 --- a/HAL_N_Middlewares/Inc/main.h +++ b/HAL_N_Middlewares/Inc/main.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -63,8 +63,9 @@ void Error_Handler(void); #define MAG_RST_GPIO_Port GPIOG #define LED_R_Pin GPIO_PIN_12 #define LED_R_GPIO_Port GPIOH -#define MAG_DR_Pin GPIO_PIN_3 -#define MAG_DR_GPIO_Port GPIOG +#define INT_MAG_Pin GPIO_PIN_3 +#define INT_MAG_GPIO_Port GPIOG +#define INT_MAG_EXTI_IRQn EXTI3_IRQn #define LED_G_Pin GPIO_PIN_11 #define LED_G_GPIO_Port GPIOH #define LED_B_Pin GPIO_PIN_10 @@ -75,6 +76,11 @@ void Error_Handler(void); #define KEY_GPIO_Port GPIOA #define CS1_ACCEL_Pin GPIO_PIN_4 #define CS1_ACCEL_GPIO_Port GPIOA +#define INT_ACCEL_Pin GPIO_PIN_4 +#define INT_ACCEL_GPIO_Port GPIOC +#define INT_ACCEL_EXTI_IRQn EXTI4_IRQn +#define INT_GYRO_Pin GPIO_PIN_5 +#define INT_GYRO_GPIO_Port GPIOC #define SERVO_Pin GPIO_PIN_9 #define SERVO_GPIO_Port GPIOE #define CS1_GYRO_Pin GPIO_PIN_0 diff --git a/HAL_N_Middlewares/Inc/rng.h b/HAL_N_Middlewares/Inc/rng.h index a9249be..25083c1 100644 --- a/HAL_N_Middlewares/Inc/rng.h +++ b/HAL_N_Middlewares/Inc/rng.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/rtc.h b/HAL_N_Middlewares/Inc/rtc.h index 95d0efb..f56d512 100644 --- a/HAL_N_Middlewares/Inc/rtc.h +++ b/HAL_N_Middlewares/Inc/rtc.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/spi.h b/HAL_N_Middlewares/Inc/spi.h index 5c35683..beb378b 100644 --- a/HAL_N_Middlewares/Inc/spi.h +++ b/HAL_N_Middlewares/Inc/spi.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/stm32f4xx_hal_conf.h b/HAL_N_Middlewares/Inc/stm32f4xx_hal_conf.h index 264135c..8399b14 100644 --- a/HAL_N_Middlewares/Inc/stm32f4xx_hal_conf.h +++ b/HAL_N_Middlewares/Inc/stm32f4xx_hal_conf.h @@ -40,9 +40,9 @@ /* #define HAL_CRYP_MODULE_ENABLED */ #define HAL_ADC_MODULE_ENABLED #define HAL_CAN_MODULE_ENABLED -/* #define HAL_CRC_MODULE_ENABLED */ +#define HAL_CRC_MODULE_ENABLED /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -/* #define HAL_DAC_MODULE_ENABLED */ +#define HAL_DAC_MODULE_ENABLED /* #define HAL_DCMI_MODULE_ENABLED */ /* #define HAL_DMA2D_MODULE_ENABLED */ /* #define HAL_ETH_MODULE_ENABLED */ diff --git a/HAL_N_Middlewares/Inc/stm32f4xx_it.h b/HAL_N_Middlewares/Inc/stm32f4xx_it.h index 74bce60..db445f8 100644 --- a/HAL_N_Middlewares/Inc/stm32f4xx_it.h +++ b/HAL_N_Middlewares/Inc/stm32f4xx_it.h @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -53,19 +53,34 @@ void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); void SysTick_Handler(void); +void EXTI3_IRQHandler(void); +void EXTI4_IRQHandler(void); void DMA1_Stream1_IRQHandler(void); +void DMA1_Stream2_IRQHandler(void); +void DMA1_Stream3_IRQHandler(void); +void DMA1_Stream4_IRQHandler(void); void CAN1_RX0_IRQHandler(void); void CAN1_RX1_IRQHandler(void); +void I2C2_EV_IRQHandler(void); +void I2C2_ER_IRQHandler(void); +void SPI1_IRQHandler(void); +void SPI2_IRQHandler(void); void USART1_IRQHandler(void); void USART3_IRQHandler(void); -void DMA2_Stream1_IRQHandler(void); +void DMA1_Stream7_IRQHandler(void); +void DMA2_Stream0_IRQHandler(void); void DMA2_Stream2_IRQHandler(void); +void DMA2_Stream3_IRQHandler(void); +void DMA2_Stream4_IRQHandler(void); void CAN2_RX0_IRQHandler(void); void CAN2_RX1_IRQHandler(void); void OTG_FS_IRQHandler(void); +void DMA2_Stream5_IRQHandler(void); void DMA2_Stream6_IRQHandler(void); void DMA2_Stream7_IRQHandler(void); void USART6_IRQHandler(void); +void I2C3_EV_IRQHandler(void); +void I2C3_ER_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/HAL_N_Middlewares/Inc/tim.h b/HAL_N_Middlewares/Inc/tim.h index dd163b6..ad0dae4 100644 --- a/HAL_N_Middlewares/Inc/tim.h +++ b/HAL_N_Middlewares/Inc/tim.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/usart.h b/HAL_N_Middlewares/Inc/usart.h index f32e55b..1928839 100644 --- a/HAL_N_Middlewares/Inc/usart.h +++ b/HAL_N_Middlewares/Inc/usart.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/usb_device.h b/HAL_N_Middlewares/Inc/usb_device.h index 34f96d5..5e8f722 100644 --- a/HAL_N_Middlewares/Inc/usb_device.h +++ b/HAL_N_Middlewares/Inc/usb_device.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/usbd_cdc_if.h b/HAL_N_Middlewares/Inc/usbd_cdc_if.h index 67c513f..a9f47c1 100644 --- a/HAL_N_Middlewares/Inc/usbd_cdc_if.h +++ b/HAL_N_Middlewares/Inc/usbd_cdc_if.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/usbd_conf.h b/HAL_N_Middlewares/Inc/usbd_conf.h index 4c39852..f74f802 100644 --- a/HAL_N_Middlewares/Inc/usbd_conf.h +++ b/HAL_N_Middlewares/Inc/usbd_conf.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Inc/usbd_desc.h b/HAL_N_Middlewares/Inc/usbd_desc.h index b26c741..8541e5e 100644 --- a/HAL_N_Middlewares/Inc/usbd_desc.h +++ b/HAL_N_Middlewares/Inc/usbd_desc.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/adc.c b/HAL_N_Middlewares/Src/adc.c index b76dbcc..864e3c4 100644 --- a/HAL_N_Middlewares/Src/adc.c +++ b/HAL_N_Middlewares/Src/adc.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -25,6 +25,7 @@ /* USER CODE END 0 */ ADC_HandleTypeDef hadc1; +DMA_HandleTypeDef hdma_adc1; /* ADC1 init function */ void MX_ADC1_Init(void) @@ -84,6 +85,26 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) /* USER CODE END ADC1_MspInit 0 */ /* ADC1 clock enable */ __HAL_RCC_ADC1_CLK_ENABLE(); + + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA2_Stream4; + hdma_adc1.Init.Channel = DMA_CHANNEL_0; + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc1.Init.Mode = DMA_NORMAL; + hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; + hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); + /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ @@ -100,6 +121,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_ADC1_CLK_DISABLE(); + + /* ADC1 DMA DeInit */ + HAL_DMA_DeInit(adcHandle->DMA_Handle); /* USER CODE BEGIN ADC1_MspDeInit 1 */ /* USER CODE END ADC1_MspDeInit 1 */ diff --git a/HAL_N_Middlewares/Src/can.c b/HAL_N_Middlewares/Src/can.c index e56dd5c..c4c0948 100644 --- a/HAL_N_Middlewares/Src/can.c +++ b/HAL_N_Middlewares/Src/can.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/crc.c b/HAL_N_Middlewares/Src/crc.c new file mode 100644 index 0000000..7683ef1 --- /dev/null +++ b/HAL_N_Middlewares/Src/crc.c @@ -0,0 +1,85 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file crc.c + * @brief This file provides code for the configuration + * of the CRC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "crc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +CRC_HandleTypeDef hcrc; + +/* CRC init function */ +void MX_CRC_Init(void) +{ + + /* USER CODE BEGIN CRC_Init 0 */ + + /* USER CODE END CRC_Init 0 */ + + /* USER CODE BEGIN CRC_Init 1 */ + + /* USER CODE END CRC_Init 1 */ + hcrc.Instance = CRC; + if (HAL_CRC_Init(&hcrc) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN CRC_Init 2 */ + + /* USER CODE END CRC_Init 2 */ + +} + +void HAL_CRC_MspInit(CRC_HandleTypeDef* crcHandle) +{ + + if(crcHandle->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspInit 0 */ + + /* USER CODE END CRC_MspInit 0 */ + /* CRC clock enable */ + __HAL_RCC_CRC_CLK_ENABLE(); + /* USER CODE BEGIN CRC_MspInit 1 */ + + /* USER CODE END CRC_MspInit 1 */ + } +} + +void HAL_CRC_MspDeInit(CRC_HandleTypeDef* crcHandle) +{ + + if(crcHandle->Instance==CRC) + { + /* USER CODE BEGIN CRC_MspDeInit 0 */ + + /* USER CODE END CRC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_CRC_CLK_DISABLE(); + /* USER CODE BEGIN CRC_MspDeInit 1 */ + + /* USER CODE END CRC_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/HAL_N_Middlewares/Src/dac.c b/HAL_N_Middlewares/Src/dac.c new file mode 100644 index 0000000..13b81ef --- /dev/null +++ b/HAL_N_Middlewares/Src/dac.c @@ -0,0 +1,116 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dac.c + * @brief This file provides code for the configuration + * of the DAC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "dac.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +DAC_HandleTypeDef hdac; + +/* DAC init function */ +void MX_DAC_Init(void) +{ + + /* USER CODE BEGIN DAC_Init 0 */ + + /* USER CODE END DAC_Init 0 */ + + DAC_ChannelConfTypeDef sConfig = {0}; + + /* USER CODE BEGIN DAC_Init 1 */ + + /* USER CODE END DAC_Init 1 */ + + /** DAC Initialization + */ + hdac.Instance = DAC; + if (HAL_DAC_Init(&hdac) != HAL_OK) + { + Error_Handler(); + } + + /** DAC channel OUT2 config + */ + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; + sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; + if (HAL_DAC_ConfigChannel(&hdac, &sConfig, DAC_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN DAC_Init 2 */ + + /* USER CODE END DAC_Init 2 */ + +} + +void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(dacHandle->Instance==DAC) + { + /* USER CODE BEGIN DAC_MspInit 0 */ + + /* USER CODE END DAC_MspInit 0 */ + /* DAC clock enable */ + __HAL_RCC_DAC_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**DAC GPIO Configuration + PA5 ------> DAC_OUT2 + */ + GPIO_InitStruct.Pin = GPIO_PIN_5; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN DAC_MspInit 1 */ + + /* USER CODE END DAC_MspInit 1 */ + } +} + +void HAL_DAC_MspDeInit(DAC_HandleTypeDef* dacHandle) +{ + + if(dacHandle->Instance==DAC) + { + /* USER CODE BEGIN DAC_MspDeInit 0 */ + + /* USER CODE END DAC_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_DAC_CLK_DISABLE(); + + /**DAC GPIO Configuration + PA5 ------> DAC_OUT2 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5); + + /* USER CODE BEGIN DAC_MspDeInit 1 */ + + /* USER CODE END DAC_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/HAL_N_Middlewares/Src/dma.c b/HAL_N_Middlewares/Src/dma.c index 3588368..a1959ee 100644 --- a/HAL_N_Middlewares/Src/dma.c +++ b/HAL_N_Middlewares/Src/dma.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -40,19 +40,40 @@ void MX_DMA_Init(void) { /* DMA controller clock enable */ - __HAL_RCC_DMA1_CLK_ENABLE(); __HAL_RCC_DMA2_CLK_ENABLE(); + __HAL_RCC_DMA1_CLK_ENABLE(); /* DMA interrupt init */ /* DMA1_Stream1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn); - /* DMA2_Stream1_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream1_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream1_IRQn); + /* DMA1_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn); + /* DMA1_Stream3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn); + /* DMA1_Stream4_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn); + /* DMA1_Stream7_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn); + /* DMA2_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); /* DMA2_Stream2_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); + /* DMA2_Stream3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); + /* DMA2_Stream4_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn); + /* DMA2_Stream5_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); /* DMA2_Stream6_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); diff --git a/HAL_N_Middlewares/Src/gpio.c b/HAL_N_Middlewares/Src/gpio.c index a27349e..922dbfc 100644 --- a/HAL_N_Middlewares/Src/gpio.c +++ b/HAL_N_Middlewares/Src/gpio.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -56,7 +56,7 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOE_CLK_ENABLE(); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(MAG_RST_GPIO_Port, MAG_RST_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(MAG_RST_GPIO_Port, MAG_RST_Pin, GPIO_PIN_SET); /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(CS1_ACCEL_GPIO_Port, CS1_ACCEL_Pin, GPIO_PIN_SET); @@ -72,10 +72,10 @@ void MX_GPIO_Init(void) HAL_GPIO_Init(MAG_RST_GPIO_Port, &GPIO_InitStruct); /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = MAG_DR_Pin; + GPIO_InitStruct.Pin = INT_MAG_Pin; GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; GPIO_InitStruct.Pull = GPIO_PULLUP; - HAL_GPIO_Init(MAG_DR_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_Init(INT_MAG_GPIO_Port, &GPIO_InitStruct); /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = KEY_Pin; @@ -90,6 +90,12 @@ void MX_GPIO_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(CS1_ACCEL_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pins : PCPin PCPin */ + GPIO_InitStruct.Pin = INT_ACCEL_Pin|INT_GYRO_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + /*Configure GPIO pin : PtPin */ GPIO_InitStruct.Pin = CS1_GYRO_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; @@ -97,6 +103,13 @@ void MX_GPIO_Init(void) GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(CS1_GYRO_GPIO_Port, &GPIO_InitStruct); + /* EXTI interrupt init*/ + HAL_NVIC_SetPriority(EXTI3_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(EXTI3_IRQn); + + HAL_NVIC_SetPriority(EXTI4_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(EXTI4_IRQn); + } /* USER CODE BEGIN 2 */ diff --git a/HAL_N_Middlewares/Src/i2c.c b/HAL_N_Middlewares/Src/i2c.c index 80a9152..0692fd5 100644 --- a/HAL_N_Middlewares/Src/i2c.c +++ b/HAL_N_Middlewares/Src/i2c.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -26,6 +26,8 @@ I2C_HandleTypeDef hi2c2; I2C_HandleTypeDef hi2c3; +DMA_HandleTypeDef hdma_i2c2_rx; +DMA_HandleTypeDef hdma_i2c2_tx; /* I2C2 init function */ void MX_I2C2_Init(void) @@ -110,6 +112,49 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) /* I2C2 clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); + + /* I2C2 DMA Init */ + /* I2C2_RX Init */ + hdma_i2c2_rx.Instance = DMA1_Stream2; + hdma_i2c2_rx.Init.Channel = DMA_CHANNEL_7; + hdma_i2c2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_i2c2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_i2c2_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_i2c2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_i2c2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_i2c2_rx.Init.Mode = DMA_NORMAL; + hdma_i2c2_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_i2c2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_i2c2_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(i2cHandle,hdmarx,hdma_i2c2_rx); + + /* I2C2_TX Init */ + hdma_i2c2_tx.Instance = DMA1_Stream7; + hdma_i2c2_tx.Init.Channel = DMA_CHANNEL_7; + hdma_i2c2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_i2c2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_i2c2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_i2c2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_i2c2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_i2c2_tx.Init.Mode = DMA_NORMAL; + hdma_i2c2_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_i2c2_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_i2c2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(i2cHandle,hdmatx,hdma_i2c2_tx); + + /* I2C2 interrupt Init */ + HAL_NVIC_SetPriority(I2C2_EV_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(I2C2_EV_IRQn); + HAL_NVIC_SetPriority(I2C2_ER_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(I2C2_ER_IRQn); /* USER CODE BEGIN I2C2_MspInit 1 */ /* USER CODE END I2C2_MspInit 1 */ @@ -142,6 +187,12 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) /* I2C3 clock enable */ __HAL_RCC_I2C3_CLK_ENABLE(); + + /* I2C3 interrupt Init */ + HAL_NVIC_SetPriority(I2C3_EV_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(I2C3_EV_IRQn); + HAL_NVIC_SetPriority(I2C3_ER_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(I2C3_ER_IRQn); /* USER CODE BEGIN I2C3_MspInit 1 */ /* USER CODE END I2C3_MspInit 1 */ @@ -167,6 +218,13 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) HAL_GPIO_DeInit(GPIOF, GPIO_PIN_1); + /* I2C2 DMA DeInit */ + HAL_DMA_DeInit(i2cHandle->hdmarx); + HAL_DMA_DeInit(i2cHandle->hdmatx); + + /* I2C2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(I2C2_EV_IRQn); + HAL_NVIC_DisableIRQ(I2C2_ER_IRQn); /* USER CODE BEGIN I2C2_MspDeInit 1 */ /* USER CODE END I2C2_MspDeInit 1 */ @@ -187,6 +245,9 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8); + /* I2C3 interrupt Deinit */ + HAL_NVIC_DisableIRQ(I2C3_EV_IRQn); + HAL_NVIC_DisableIRQ(I2C3_ER_IRQn); /* USER CODE BEGIN I2C3_MspDeInit 1 */ /* USER CODE END I2C3_MspDeInit 1 */ diff --git a/HAL_N_Middlewares/Src/rng.c b/HAL_N_Middlewares/Src/rng.c index 8003a99..a1238ca 100644 --- a/HAL_N_Middlewares/Src/rng.c +++ b/HAL_N_Middlewares/Src/rng.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/rtc.c b/HAL_N_Middlewares/Src/rtc.c index 81e0bdd..a72520c 100644 --- a/HAL_N_Middlewares/Src/rtc.c +++ b/HAL_N_Middlewares/Src/rtc.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/spi.c b/HAL_N_Middlewares/Src/spi.c index 4586ed9..5f1bce7 100644 --- a/HAL_N_Middlewares/Src/spi.c +++ b/HAL_N_Middlewares/Src/spi.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -26,6 +26,10 @@ SPI_HandleTypeDef hspi1; SPI_HandleTypeDef hspi2; +DMA_HandleTypeDef hdma_spi1_rx; +DMA_HandleTypeDef hdma_spi1_tx; +DMA_HandleTypeDef hdma_spi2_rx; +DMA_HandleTypeDef hdma_spi2_tx; /* SPI1 init function */ void MX_SPI1_Init(void) @@ -125,6 +129,49 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /* SPI1 DMA Init */ + /* SPI1_RX Init */ + hdma_spi1_rx.Instance = DMA2_Stream0; + hdma_spi1_rx.Init.Channel = DMA_CHANNEL_3; + hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_spi1_rx.Init.Mode = DMA_NORMAL; + hdma_spi1_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_spi1_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_spi1_rx.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_spi1_rx.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi1_rx); + + /* SPI1_TX Init */ + hdma_spi1_tx.Instance = DMA2_Stream3; + hdma_spi1_tx.Init.Channel = DMA_CHANNEL_3; + hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_spi1_tx.Init.Mode = DMA_NORMAL; + hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi1_tx); + + /* SPI1 interrupt Init */ + HAL_NVIC_SetPriority(SPI1_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(SPI1_IRQn); /* USER CODE BEGIN SPI1_MspInit 1 */ /* USER CODE END SPI1_MspInit 1 */ @@ -150,6 +197,52 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /* SPI2 DMA Init */ + /* SPI2_RX Init */ + hdma_spi2_rx.Instance = DMA1_Stream3; + hdma_spi2_rx.Init.Channel = DMA_CHANNEL_0; + hdma_spi2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_spi2_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi2_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_spi2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_spi2_rx.Init.Mode = DMA_NORMAL; + hdma_spi2_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_spi2_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_spi2_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_spi2_rx.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_spi2_rx.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_spi2_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi2_rx); + + /* SPI2_TX Init */ + hdma_spi2_tx.Instance = DMA1_Stream4; + hdma_spi2_tx.Init.Channel = DMA_CHANNEL_0; + hdma_spi2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_spi2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_spi2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_spi2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_spi2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_spi2_tx.Init.Mode = DMA_NORMAL; + hdma_spi2_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_spi2_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_spi2_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_spi2_tx.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_spi2_tx.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_spi2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi2_tx); + + /* SPI2 interrupt Init */ + HAL_NVIC_SetPriority(SPI2_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(SPI2_IRQn); /* USER CODE BEGIN SPI2_MspInit 1 */ /* USER CODE END SPI2_MspInit 1 */ @@ -176,6 +269,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7); + /* SPI1 DMA DeInit */ + HAL_DMA_DeInit(spiHandle->hdmarx); + HAL_DMA_DeInit(spiHandle->hdmatx); + + /* SPI1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(SPI1_IRQn); /* USER CODE BEGIN SPI1_MspDeInit 1 */ /* USER CODE END SPI1_MspDeInit 1 */ @@ -195,6 +294,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) */ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); + /* SPI2 DMA DeInit */ + HAL_DMA_DeInit(spiHandle->hdmarx); + HAL_DMA_DeInit(spiHandle->hdmatx); + + /* SPI2 interrupt Deinit */ + HAL_NVIC_DisableIRQ(SPI2_IRQn); /* USER CODE BEGIN SPI2_MspDeInit 1 */ /* USER CODE END SPI2_MspDeInit 1 */ diff --git a/HAL_N_Middlewares/Src/stm32f4xx_hal_msp.c b/HAL_N_Middlewares/Src/stm32f4xx_hal_msp.c index fa32802..ed524b2 100644 --- a/HAL_N_Middlewares/Src/stm32f4xx_hal_msp.c +++ b/HAL_N_Middlewares/Src/stm32f4xx_hal_msp.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/stm32f4xx_it.c b/HAL_N_Middlewares/Src/stm32f4xx_it.c index 1616e15..f44f90b 100644 --- a/HAL_N_Middlewares/Src/stm32f4xx_it.c +++ b/HAL_N_Middlewares/Src/stm32f4xx_it.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -58,8 +58,19 @@ /* External variables --------------------------------------------------------*/ extern PCD_HandleTypeDef hpcd_USB_OTG_FS; +extern DMA_HandleTypeDef hdma_adc1; extern CAN_HandleTypeDef hcan1; extern CAN_HandleTypeDef hcan2; +extern DMA_HandleTypeDef hdma_i2c2_rx; +extern DMA_HandleTypeDef hdma_i2c2_tx; +extern I2C_HandleTypeDef hi2c2; +extern I2C_HandleTypeDef hi2c3; +extern DMA_HandleTypeDef hdma_spi1_rx; +extern DMA_HandleTypeDef hdma_spi1_tx; +extern DMA_HandleTypeDef hdma_spi2_rx; +extern DMA_HandleTypeDef hdma_spi2_tx; +extern SPI_HandleTypeDef hspi1; +extern SPI_HandleTypeDef hspi2; extern DMA_HandleTypeDef hdma_usart1_tx; extern DMA_HandleTypeDef hdma_usart1_rx; extern DMA_HandleTypeDef hdma_usart3_rx; @@ -100,9 +111,9 @@ void HardFault_Handler(void) /* USER CODE END HardFault_IRQn 0 */ while (1) { + /* USER CODE BEGIN W1_HardFault_IRQn 0 */ // 发生hardfault,点击step over会自动跳转回出错的指令,方便调试 asm("bx lr"); - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ /* USER CODE END W1_HardFault_IRQn 0 */ } } @@ -194,6 +205,34 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32f4xx.s). */ /******************************************************************************/ +/** + * @brief This function handles EXTI line3 interrupt. + */ +void EXTI3_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI3_IRQn 0 */ + + /* USER CODE END EXTI3_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(INT_MAG_Pin); + /* USER CODE BEGIN EXTI3_IRQn 1 */ + + /* USER CODE END EXTI3_IRQn 1 */ +} + +/** + * @brief This function handles EXTI line4 interrupt. + */ +void EXTI4_IRQHandler(void) +{ + /* USER CODE BEGIN EXTI4_IRQn 0 */ + + /* USER CODE END EXTI4_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(INT_ACCEL_Pin); + /* USER CODE BEGIN EXTI4_IRQn 1 */ + + /* USER CODE END EXTI4_IRQn 1 */ +} + /** * @brief This function handles DMA1 stream1 global interrupt. */ @@ -208,6 +247,48 @@ void DMA1_Stream1_IRQHandler(void) /* USER CODE END DMA1_Stream1_IRQn 1 */ } +/** + * @brief This function handles DMA1 stream2 global interrupt. + */ +void DMA1_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */ + + /* USER CODE END DMA1_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_i2c2_rx); + /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */ + + /* USER CODE END DMA1_Stream2_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream3 global interrupt. + */ +void DMA1_Stream3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream3_IRQn 0 */ + + /* USER CODE END DMA1_Stream3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi2_rx); + /* USER CODE BEGIN DMA1_Stream3_IRQn 1 */ + + /* USER CODE END DMA1_Stream3_IRQn 1 */ +} + +/** + * @brief This function handles DMA1 stream4 global interrupt. + */ +void DMA1_Stream4_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */ + + /* USER CODE END DMA1_Stream4_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi2_tx); + /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */ + + /* USER CODE END DMA1_Stream4_IRQn 1 */ +} + /** * @brief This function handles CAN1 RX0 interrupts. */ @@ -236,6 +317,62 @@ void CAN1_RX1_IRQHandler(void) /* USER CODE END CAN1_RX1_IRQn 1 */ } +/** + * @brief This function handles I2C2 event interrupt. + */ +void I2C2_EV_IRQHandler(void) +{ + /* USER CODE BEGIN I2C2_EV_IRQn 0 */ + + /* USER CODE END I2C2_EV_IRQn 0 */ + HAL_I2C_EV_IRQHandler(&hi2c2); + /* USER CODE BEGIN I2C2_EV_IRQn 1 */ + + /* USER CODE END I2C2_EV_IRQn 1 */ +} + +/** + * @brief This function handles I2C2 error interrupt. + */ +void I2C2_ER_IRQHandler(void) +{ + /* USER CODE BEGIN I2C2_ER_IRQn 0 */ + + /* USER CODE END I2C2_ER_IRQn 0 */ + HAL_I2C_ER_IRQHandler(&hi2c2); + /* USER CODE BEGIN I2C2_ER_IRQn 1 */ + + /* USER CODE END I2C2_ER_IRQn 1 */ +} + +/** + * @brief This function handles SPI1 global interrupt. + */ +void SPI1_IRQHandler(void) +{ + /* USER CODE BEGIN SPI1_IRQn 0 */ + + /* USER CODE END SPI1_IRQn 0 */ + HAL_SPI_IRQHandler(&hspi1); + /* USER CODE BEGIN SPI1_IRQn 1 */ + + /* USER CODE END SPI1_IRQn 1 */ +} + +/** + * @brief This function handles SPI2 global interrupt. + */ +void SPI2_IRQHandler(void) +{ + /* USER CODE BEGIN SPI2_IRQn 0 */ + + /* USER CODE END SPI2_IRQn 0 */ + HAL_SPI_IRQHandler(&hspi2); + /* USER CODE BEGIN SPI2_IRQn 1 */ + + /* USER CODE END SPI2_IRQn 1 */ +} + /** * @brief This function handles USART1 global interrupt. */ @@ -265,17 +402,31 @@ void USART3_IRQHandler(void) } /** - * @brief This function handles DMA2 stream1 global interrupt. + * @brief This function handles DMA1 stream7 global interrupt. */ -void DMA2_Stream1_IRQHandler(void) +void DMA1_Stream7_IRQHandler(void) { - /* USER CODE BEGIN DMA2_Stream1_IRQn 0 */ + /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */ - /* USER CODE END DMA2_Stream1_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart6_rx); - /* USER CODE BEGIN DMA2_Stream1_IRQn 1 */ + /* USER CODE END DMA1_Stream7_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_i2c2_tx); + /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */ - /* USER CODE END DMA2_Stream1_IRQn 1 */ + /* USER CODE END DMA1_Stream7_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream0 global interrupt. + */ +void DMA2_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */ + + /* USER CODE END DMA2_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi1_rx); + /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */ + + /* USER CODE END DMA2_Stream0_IRQn 1 */ } /** @@ -286,12 +437,40 @@ void DMA2_Stream2_IRQHandler(void) /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ /* USER CODE END DMA2_Stream2_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart1_rx); + HAL_DMA_IRQHandler(&hdma_usart6_rx); /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ /* USER CODE END DMA2_Stream2_IRQn 1 */ } +/** + * @brief This function handles DMA2 stream3 global interrupt. + */ +void DMA2_Stream3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */ + + /* USER CODE END DMA2_Stream3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_spi1_tx); + /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */ + + /* USER CODE END DMA2_Stream3_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream4 global interrupt. + */ +void DMA2_Stream4_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream4_IRQn 0 */ + + /* USER CODE END DMA2_Stream4_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc1); + /* USER CODE BEGIN DMA2_Stream4_IRQn 1 */ + + /* USER CODE END DMA2_Stream4_IRQn 1 */ +} + /** * @brief This function handles CAN2 RX0 interrupts. */ @@ -334,6 +513,20 @@ void OTG_FS_IRQHandler(void) /* USER CODE END OTG_FS_IRQn 1 */ } +/** + * @brief This function handles DMA2 stream5 global interrupt. + */ +void DMA2_Stream5_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream5_IRQn 0 */ + + /* USER CODE END DMA2_Stream5_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_rx); + /* USER CODE BEGIN DMA2_Stream5_IRQn 1 */ + + /* USER CODE END DMA2_Stream5_IRQn 1 */ +} + /** * @brief This function handles DMA2 stream6 global interrupt. */ @@ -376,6 +569,34 @@ void USART6_IRQHandler(void) /* USER CODE END USART6_IRQn 1 */ } +/** + * @brief This function handles I2C3 event interrupt. + */ +void I2C3_EV_IRQHandler(void) +{ + /* USER CODE BEGIN I2C3_EV_IRQn 0 */ + + /* USER CODE END I2C3_EV_IRQn 0 */ + HAL_I2C_EV_IRQHandler(&hi2c3); + /* USER CODE BEGIN I2C3_EV_IRQn 1 */ + + /* USER CODE END I2C3_EV_IRQn 1 */ +} + +/** + * @brief This function handles I2C3 error interrupt. + */ +void I2C3_ER_IRQHandler(void) +{ + /* USER CODE BEGIN I2C3_ER_IRQn 0 */ + + /* USER CODE END I2C3_ER_IRQn 0 */ + HAL_I2C_ER_IRQHandler(&hi2c3); + /* USER CODE BEGIN I2C3_ER_IRQn 1 */ + + /* USER CODE END I2C3_ER_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/HAL_N_Middlewares/Src/tim.c b/HAL_N_Middlewares/Src/tim.c index ae82a9c..004b62f 100644 --- a/HAL_N_Middlewares/Src/tim.c +++ b/HAL_N_Middlewares/Src/tim.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -423,20 +423,13 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) PE11 ------> TIM1_CH2 PE14 ------> TIM1_CH4 */ - GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_11|GPIO_PIN_14; + GPIO_InitStruct.Pin = GPIO_PIN_13|SERVO_Pin|GPIO_PIN_11|GPIO_PIN_14; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - GPIO_InitStruct.Pin = SERVO_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF1_TIM1; - HAL_GPIO_Init(SERVO_GPIO_Port, &GPIO_InitStruct); - /* USER CODE BEGIN TIM1_MspPostInit 1 */ /* USER CODE END TIM1_MspPostInit 1 */ diff --git a/HAL_N_Middlewares/Src/usart.c b/HAL_N_Middlewares/Src/usart.c index 31895f5..8595e32 100644 --- a/HAL_N_Middlewares/Src/usart.c +++ b/HAL_N_Middlewares/Src/usart.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -173,7 +173,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); /* USART1_RX Init */ - hdma_usart1_rx.Instance = DMA2_Stream2; + hdma_usart1_rx.Instance = DMA2_Stream5; hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; @@ -227,7 +227,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_usart3_rx.Init.Mode = DMA_NORMAL; - hdma_usart3_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH; + hdma_usart3_rx.Init.Priority = DMA_PRIORITY_LOW; hdma_usart3_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) { @@ -265,7 +265,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) /* USART6 DMA Init */ /* USART6_RX Init */ - hdma_usart6_rx.Instance = DMA2_Stream1; + hdma_usart6_rx.Instance = DMA2_Stream2; hdma_usart6_rx.Init.Channel = DMA_CHANNEL_5; hdma_usart6_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; hdma_usart6_rx.Init.PeriphInc = DMA_PINC_DISABLE; diff --git a/HAL_N_Middlewares/Src/usb_device.c b/HAL_N_Middlewares/Src/usb_device.c index b3cd731..1c91d19 100644 --- a/HAL_N_Middlewares/Src/usb_device.c +++ b/HAL_N_Middlewares/Src/usb_device.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/usbd_cdc_if.c b/HAL_N_Middlewares/Src/usbd_cdc_if.c index 7b54780..2cb391e 100644 --- a/HAL_N_Middlewares/Src/usbd_cdc_if.c +++ b/HAL_N_Middlewares/Src/usbd_cdc_if.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/usbd_conf.c b/HAL_N_Middlewares/Src/usbd_conf.c index 4cfe7d8..efde0dd 100644 --- a/HAL_N_Middlewares/Src/usbd_conf.c +++ b/HAL_N_Middlewares/Src/usbd_conf.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/HAL_N_Middlewares/Src/usbd_desc.c b/HAL_N_Middlewares/Src/usbd_desc.c index 89ab7d4..16f1f4e 100644 --- a/HAL_N_Middlewares/Src/usbd_desc.c +++ b/HAL_N_Middlewares/Src/usbd_desc.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2023 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file diff --git a/Makefile b/Makefile index 9de7503..21b9c0b 100644 --- a/Makefile +++ b/Makefile @@ -122,6 +122,7 @@ modules/algorithm/user_lib.c \ modules/imu/BMI088driver.c \ modules/imu/BMI088Middleware.c \ modules/imu/ins_task.c \ +modules/ist8310/ist8310.c \ modules/led/led_task.c \ modules/master_machine/master_process.c \ modules/master_machine/seasky_protocol.c \ @@ -132,7 +133,7 @@ modules/motor/step_motor/step_motor.c \ modules/motor/servo_motor/servo_motor.c \ modules/motor/motor_task.c \ modules/oled/oled.c \ -modules/referee/crc.c \ +modules/referee/crc_ref.c \ modules/referee/referee.c \ modules/referee/referee_UI.c \ modules/referee/referee_communication.c \ @@ -239,6 +240,7 @@ C_INCLUDES = \ -Ibsp \ -Imodules/algorithm \ -Imodules/imu \ +-Imodules/ist8310 \ -Imodules/led \ -Imodules/master_machine \ -Imodules/motor/DJImotor \ diff --git a/assets/00937839b59a4c039ee8ecb8a5136e3c.png b/assets/00937839b59a4c039ee8ecb8a5136e3c.png new file mode 100644 index 0000000000000000000000000000000000000000..a890de4c23021a81a8d05ad5c0bbc09194caf0b7 GIT binary patch literal 139181 zcmZ_0bx_+;*ELEA5HwgR7Tl${1cw3zin|moP#l63x1cTVR@|Yu6)6y)XmN^LDBeN~ z#VK;r=lkyay!Vegdoq*xC1U`Jll#hbJBDAxbt#k@OHH^t3QgsJL5jie_ip;m zeSPmvBnCFK-yse_2YXbt5=#wq<%<8So7_0Vxz*+IDo?^kIK{h+#?N;2lBT)F+h=cb zyu;_$%`YF5$-Zz9>30z}!2dEhK6BD`s63XAM;8?5zgCF>fx&=%Dv19vdTSggGO4k0 zEkOhQzXpc3^COx6Ye|i$h9gFLu1f#wHvk~W8U>8xzcylo4u;xrbABpG4gIeH!LIoK z^#F=v!;NYv@HBmO=6{?(xdQ-+V&!7|*90;`fndtmvEzgPk_GcDS$h5zH+iY)4b7Pywg%TzGbD=iV0?}_ay2`vQ}yv=etup>7IuE1z1$np3r-utt+SiT_vdC42J^W(pCRBt0h^H|EVPJT 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zQo>XR3DwrhC~@Turv|t^XYm6<4`OJm=;V_?CQmS=rtxr7`E?6mb;aeL8F-($<>s7@ z?wK?0r>|z;zWJ`j=ed99oA{5X{Kuf8bWdpRbNr^d+Q z8B%WQXr;_1@3jNM*OtcPPG|8e_z&yL23wmuchxTAvE|Ai{50||WvHO+EOd{TpXNGO ze|B1Kg1N#gHODCc3;Q0@W)x1uQ^(qBw_3JCKB&!WCGVx>uT^qKt#G^fJ@-!+M&NM7 zJS$vWD0H#O<3ppoHDbv5iXAW5v1|SWuqwy0o!KIe5Y4tOD=qS^ka|22xBN9SoGPIY zOs}2eo&9lp80(P)B$9Fc>q~uqQ6j~u0lart|Hv$t%+;1vkM47SwGY_e6t$G7WcEGf z=2svd2y9~bPPWDB4fcKxd4_i0)KYt&q{u%8^e#b}c2Jm{y*aEy}-B!*aXULWn<GPIO_Pin==GPIO_Pin && gpio->gpio_model_callback!=NULL) + { + gpio->gpio_model_callback(gpio); + return; + } + } } - GPIOInstance *GPIORegister(GPIO_Init_Config_s *GPIO_config) { GPIOInstance *ins=(GPIOInstance*)malloc(sizeof(GPIOInstance)); @@ -18,6 +34,8 @@ GPIOInstance *GPIORegister(GPIO_Init_Config_s *GPIO_config) ins->GPIOx=GPIO_config->GPIOx; ins->GPIO_Pin=GPIO_config->GPIO_Pin; + ins->pin_state=GPIO_config->pin_state; + ins->exti_mode=GPIO_config->exti_mode; ins->id=GPIO_config->id; ins->gpio_model_callback=GPIO_config->gpio_model_callback; diff --git a/bsp/gpio/bsp_gpio.h b/bsp/gpio/bsp_gpio.h index 7d5272e..ced389c 100644 --- a/bsp/gpio/bsp_gpio.h +++ b/bsp/gpio/bsp_gpio.h @@ -4,35 +4,82 @@ #define GPIO_MX_DEVICE_NUM 10 /** - * @brief GPIO实例结构体定义 - * + * @brief 用于判断中断来源,注意和CUBEMX中配置一致 + * */ -typedef struct tmpgpio +typedef enum { - GPIO_TypeDef *GPIOx; - uint16_t GPIO_Pin; - void* id; - void (*gpio_model_callback)(struct tmpgpio*); // 随便取个名字当临时声明 + GPIO_EXTI_MODE_RISING, + GPIO_EXTI_MODE_FALLING, + GPIO_EXTI_MODE_RISING_FALLING, + GPIO_EXTI_MODE_NONE, +} GPIO_EXTI_MODE_e; + +/** + * @brief GPIO实例结构体定义 + * + */ +typedef struct tmpgpio +{ + GPIO_TypeDef *GPIOx; // GPIOA,GPIOB,GPIOC... + GPIO_PinState pin_state; // 引脚状态,Set,Reset;not frequently used + GPIO_EXTI_MODE_e exti_mode; // 外部中断模式 not frequently used + uint16_t GPIO_Pin; // 引脚号 + // 随便取个名字当临时声明 + void (*gpio_model_callback)(struct tmpgpio *); // exti中断回调函数 + void *id; // 区分不同的GPIO实例 + } GPIOInstance; /** * @brief GPIO初始化配置结构体定义 - * + * */ typedef struct { - GPIO_TypeDef *GPIOx; - uint16_t GPIO_Pin; - void* id; - void (*gpio_model_callback)(GPIOInstance*); + GPIO_TypeDef *GPIOx; // GPIOA,GPIOB,GPIOC... + GPIO_PinState pin_state; // 引脚状态,Set,Reset not frequently used + GPIO_EXTI_MODE_e exti_mode; // 外部中断模式 not frequently used + uint16_t GPIO_Pin; // 引脚号 + + void (*gpio_model_callback)(GPIOInstance *); // exti中断回调函数 + void *id; // 区分不同的GPIO实例 + } GPIO_Init_Config_s; -GPIOInstance* GPIORegister(GPIO_Init_Config_s* GPIO_config); +/** + * @brief 注册GPIO实例 + * + * @param GPIO_config + * @return GPIOInstance* + */ +GPIOInstance *GPIORegister(GPIO_Init_Config_s *GPIO_config); -void GPIOToggel(GPIOInstance* _instance); +/** + * @brief GPIO API,切换GPIO电平 + * + * @param _instance + */ +void GPIOToggel(GPIOInstance *_instance); -void GPIOSet(GPIOInstance* _instance); +/** + * @brief 设置GPIO电平 + * + * @param _instance + */ +void GPIOSet(GPIOInstance *_instance); -void GPIOReset(GPIOInstance* _instance); +/** + * @brief 复位GPIO电平 + * + * @param _instance + */ +void GPIOReset(GPIOInstance *_instance); -GPIO_PinState GPIORead(GPIOInstance* _instance); \ No newline at end of file +/** + * @brief 读取GPIO电平 + * + * @param _instance + * @return GPIO_PinState + */ +GPIO_PinState GPIORead(GPIOInstance *_instance); \ No newline at end of file diff --git a/bsp/gpio/bsp_gpio.md b/bsp/gpio/bsp_gpio.md index e69de29..4d604f0 100644 --- a/bsp/gpio/bsp_gpio.md +++ b/bsp/gpio/bsp_gpio.md @@ -0,0 +1,3 @@ +![image-20230202151939109](../../assets/image-20230202151939109.png) + +![img](../../assets/00937839b59a4c039ee8ecb8a5136e3c.png) \ No newline at end of file diff --git a/modules/ist8310/ist8310.h b/modules/ist8310/ist8310.h index f87285b..ee57556 100644 --- a/modules/ist8310/ist8310.h +++ b/modules/ist8310/ist8310.h @@ -1,5 +1,5 @@ #pragma once -#include "bsp_i2c.h" +#include "bsp_iic.h" #include "stdint.h" diff --git a/modules/referee/crc.c b/modules/referee/crc_ref.c similarity index 99% rename from modules/referee/crc.c rename to modules/referee/crc_ref.c index a0cd359..a18fc78 100644 --- a/modules/referee/crc.c +++ b/modules/referee/crc_ref.c @@ -1,4 +1,4 @@ -#include "crc.h" +#include "crc_ref.h" #include //裁判系统官方CRC校验 diff --git a/modules/referee/crc.h b/modules/referee/crc_ref.h similarity index 100% rename from modules/referee/crc.h rename to modules/referee/crc_ref.h