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修改IMU

This commit is contained in:
zcj 2024-12-25 15:25:25 +08:00
parent dc1c5d4bda
commit 633e3f8469
27 changed files with 11910 additions and 12718 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
CMakeLists.txt
View File

@ -63,8 +63,7 @@ include_directories(Middlewares/ST/ARM/DSP/Inc)
add_definitions(-DDEBUG -DUSE_HAL_DRIVER -DSTM32H723xx)
file(GLOB_RECURSE SOURCES "Core/*.*" "Middlewares/*.*" "Drivers/*.*" "USB_DEVICE/*.*"
"bsp/*.*" "application/*.*" "modules/*.*")
file(GLOB_RECURSE SOURCES "Core/*.*" "Middlewares/*.*" "Drivers/*.*" "USB_DEVICE/*.*" "application/*.*" "modules/*.*" "bsp/*.*")
set(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32H723VGTX_FLASH.ld)

3
Core/Inc/stm32h7xx_it.h
View File

@ -63,6 +63,7 @@ void FDCAN1_IT0_IRQHandler(void);
void FDCAN2_IT0_IRQHandler(void);
void FDCAN1_IT1_IRQHandler(void);
void FDCAN2_IT1_IRQHandler(void);
void SPI1_IRQHandler(void);
void USART1_IRQHandler(void);
void USART2_IRQHandler(void);
void USART3_IRQHandler(void);
@ -72,6 +73,8 @@ void UART5_IRQHandler(void);
void DMA2_Stream0_IRQHandler(void);
void DMA2_Stream1_IRQHandler(void);
void DMA2_Stream2_IRQHandler(void);
void DMA2_Stream3_IRQHandler(void);
void DMA2_Stream4_IRQHandler(void);
void FDCAN_CAL_IRQHandler(void);
void OTG_HS_EP1_OUT_IRQHandler(void);
void OTG_HS_EP1_IN_IRQHandler(void);

56
Core/Src/spi.c
View File

@ -26,6 +26,8 @@
SPI_HandleTypeDef hspi1;
SPI_HandleTypeDef hspi2;
DMA_HandleTypeDef hdma_spi1_rx;
DMA_HandleTypeDef hdma_spi1_tx;
/* SPI1 init function */
void MX_SPI1_Init(void)
@ -41,11 +43,11 @@ void MX_SPI1_Init(void)
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@ -156,6 +158,46 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* SPI1 DMA Init */
/* SPI1_RX Init */
hdma_spi1_rx.Instance = DMA2_Stream3;
hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX;
hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_spi1_rx.Init.Mode = DMA_NORMAL;
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_LOW;
hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(spiHandle,hdmarx,hdma_spi1_rx);
/* SPI1_TX Init */
hdma_spi1_tx.Instance = DMA2_Stream4;
hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_spi1_tx.Init.Mode = DMA_NORMAL;
hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
{
Error_Handler();
}
__HAL_LINKDMA(spiHandle,hdmatx,hdma_spi1_tx);
/* SPI1 interrupt Init */
HAL_NVIC_SetPriority(SPI1_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(SPI1_IRQn);
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
@ -225,6 +267,12 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4);
/* SPI1 DMA DeInit */
HAL_DMA_DeInit(spiHandle->hdmarx);
HAL_DMA_DeInit(spiHandle->hdmatx);
/* SPI1 interrupt Deinit */
HAL_NVIC_DisableIRQ(SPI1_IRQn);
/* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */

45
Core/Src/stm32h7xx_it.c
View File

@ -59,6 +59,9 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
extern FDCAN_HandleTypeDef hfdcan1;
extern FDCAN_HandleTypeDef hfdcan2;
extern FDCAN_HandleTypeDef hfdcan3;
extern DMA_HandleTypeDef hdma_spi1_rx;
extern DMA_HandleTypeDef hdma_spi1_tx;
extern SPI_HandleTypeDef hspi1;
extern DMA_HandleTypeDef hdma_uart5_rx;
extern DMA_HandleTypeDef hdma_uart7_rx;
extern DMA_HandleTypeDef hdma_uart7_tx;
@ -334,6 +337,20 @@ void FDCAN2_IT1_IRQHandler(void)
/* USER CODE END FDCAN2_IT1_IRQn 1 */
}
/**
* @brief This function handles SPI1 global interrupt.
*/
void SPI1_IRQHandler(void)
{
/* USER CODE BEGIN SPI1_IRQn 0 */
/* USER CODE END SPI1_IRQn 0 */
HAL_SPI_IRQHandler(&hspi1);
/* USER CODE BEGIN SPI1_IRQn 1 */
/* USER CODE END SPI1_IRQn 1 */
}
/**
* @brief This function handles USART1 global interrupt.
*/
@ -460,6 +477,34 @@ void DMA2_Stream2_IRQHandler(void)
/* USER CODE END DMA2_Stream2_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream3 global interrupt.
*/
void DMA2_Stream3_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream3_IRQn 0 */
/* USER CODE END DMA2_Stream3_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_spi1_rx);
/* USER CODE BEGIN DMA2_Stream3_IRQn 1 */
/* USER CODE END DMA2_Stream3_IRQn 1 */
}
/**
* @brief This function handles DMA2 stream4 global interrupt.
*/
void DMA2_Stream4_IRQHandler(void)
{
/* USER CODE BEGIN DMA2_Stream4_IRQn 0 */
/* USER CODE END DMA2_Stream4_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_spi1_tx);
/* USER CODE BEGIN DMA2_Stream4_IRQn 1 */
/* USER CODE END DMA2_Stream4_IRQn 1 */
}
/**
* @brief This function handles FDCAN calibration unit interrupt.
*/

69
Core/Src/tim.c
View File

@ -176,7 +176,6 @@ void MX_TIM3_Init(void)
/* USER CODE END TIM3_Init 0 */
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
@ -184,25 +183,15 @@ void MX_TIM3_Init(void)
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
htim3.Init.Prescaler = 0;
htim3.Init.Prescaler = 24-1;
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
htim3.Init.Period = 65535;
htim3.Init.Period = 10000-1;
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
{
Error_Handler();
}
if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
{
Error_Handler();
}
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_EXTERNAL1;
sSlaveConfig.InputTrigger = TIM_TS_ITR0;
if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
@ -304,17 +293,6 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
/* USER CODE END TIM2_MspInit 1 */
}
else if(tim_baseHandle->Instance==TIM3)
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
else if(tim_baseHandle->Instance==TIM12)
{
/* USER CODE BEGIN TIM12_MspInit 0 */
@ -327,6 +305,22 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
/* USER CODE END TIM12_MspInit 1 */
}
}
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle)
{
if(tim_pwmHandle->Instance==TIM3)
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* TIM3 clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
@ -444,17 +438,6 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
/* USER CODE END TIM2_MspDeInit 1 */
}
else if(tim_baseHandle->Instance==TIM3)
{
/* USER CODE BEGIN TIM3_MspDeInit 0 */
/* USER CODE END TIM3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM3_CLK_DISABLE();
/* USER CODE BEGIN TIM3_MspDeInit 1 */
/* USER CODE END TIM3_MspDeInit 1 */
}
else if(tim_baseHandle->Instance==TIM12)
{
/* USER CODE BEGIN TIM12_MspDeInit 0 */
@ -468,6 +451,22 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
}
}
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle)
{
if(tim_pwmHandle->Instance==TIM3)
{
/* USER CODE BEGIN TIM3_MspDeInit 0 */
/* USER CODE END TIM3_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM3_CLK_DISABLE();
/* USER CODE BEGIN TIM3_MspDeInit 1 */
/* USER CODE END TIM3_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

4
Core/Src/usart.c
View File

@ -55,9 +55,9 @@ void MX_UART5_Init(void)
/* USER CODE END UART5_Init 1 */
huart5.Instance = UART5;
huart5.Init.BaudRate = 100000;
huart5.Init.WordLength = UART_WORDLENGTH_8B;
huart5.Init.WordLength = UART_WORDLENGTH_9B;
huart5.Init.StopBits = UART_STOPBITS_1;
huart5.Init.Parity = UART_PARITY_NONE;
huart5.Init.Parity = UART_PARITY_EVEN;
huart5.Init.Mode = UART_MODE_TX_RX;
huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart5.Init.OverSampling = UART_OVERSAMPLING_16;

5
application/robot_task.h
View File

@ -36,8 +36,9 @@ void StartUITASK(void const *argument);
*/
void OSTaskInit()
{
osThreadDef(instask, StartINSTASK, osPriorityAboveNormal, 0, 1024);
insTaskHandle = osThreadCreate(osThread(instask), NULL); // 由于是阻塞读取传感器,为姿态解算设置较高优先级,确保以1khz的频率执行
//@todo:先注释掉INS任务，因为工程不需要陀螺仪数据
// osThreadDef(instask, StartINSTASK, osPriorityAboveNormal, 0, 1024);
// insTaskHandle = osThreadCreate(osThread(instask), NULL); // 由于是阻塞读取传感器,为姿态解算设置较高优先级,确保以1khz的频率执行
// 后续修改为读取传感器数据准备好的中断处理,
osThreadDef(motortask, StartMOTORTASK, osPriorityNormal, 0, 256);

1
bsp/usart/bsp_usart.c
View File

@ -133,6 +133,7 @@ void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
HAL_UARTEx_ReceiveToIdle_DMA(usart_instance[i]->usart_handle, usart_instance[i]->recv_buff, usart_instance[i]->recv_buff_size);
__HAL_DMA_DISABLE_IT(usart_instance[i]->usart_handle->hdmarx, DMA_IT_HT);
LOGWARNING("[bsp_usart] USART error callback triggered, instance idx [%d]", i);
return;
}
}

2
bsp/usart/bsp_usart.h
View File

@ -4,7 +4,7 @@
#include <stdint.h>
#include "main.h"
#define DEVICE_USART_CNT 3 // C板至多分配3个串口
#define DEVICE_USART_CNT 6 // DM_MC02板至多分配6个串口
#define USART_RXBUFF_LIMIT 256 // 如果协议需要更大的buff,请修改这里
// 模块回调函数,用于解析协议

BIN
cmake-build-debug/.ninja_deps
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cmake-build-debug/.ninja_log
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-- Minimal optimization, debug info included
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/*********************************************************************
* (c) SEGGER Microcontroller GmbH *
* The Embedded Experts *
* www.segger.com *
**********************************************************************
File : D:/RM/@RM2025/scara_engineering/debug.jdebug
Created : 22 Dec 2024 21:13
Ozone Version : V3.32
*/
/*********************************************************************
*
* OnProjectLoad
*
* Function description
* Project load routine. Required.
*
**********************************************************************
*/
void OnProjectLoad (void) {
//
// Dialog-generated settings
//
Project.AddPathSubstitute ("D:/RM/@RM2025/scara_engineering", "$(ProjectDir)");
Project.AddPathSubstitute ("d:/rm/@rm2025/scara_engineering", "$(ProjectDir)");
Project.SetDevice ("STM32H723VG");
Project.SetHostIF ("USB", "69651947");
Project.SetTargetIF ("SWD");
Project.SetTIFSpeed ("4 MHz");
Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M7F.svd");
Project.AddSvdFile ("$(InstallDir)/Config/Peripherals/STM32H723.svd");
//
// User settings
//
File.Open ("$(ProjectDir)/cmake-build-debug/scara_engineering.elf");
}
/*********************************************************************
*
* OnStartupComplete
*
* Function description
* Called when program execution has reached/passed
* the startup completion point. Optional.
*
**********************************************************************
*/
//void OnStartupComplete (void) {
//}
/*********************************************************************
*
* TargetReset
*
* Function description
* Replaces the default target device reset routine. Optional.
*
* Notes
* This example demonstrates the usage when
* debugging an application in RAM on a Cortex-M target device.
*
**********************************************************************
*/
//void TargetReset (void) {
//
// unsigned int SP;
// unsigned int PC;
// unsigned int VectorTableAddr;
//
// VectorTableAddr = Elf.GetBaseAddr();
// //
// // Set up initial stack pointer
// //
// if (VectorTableAddr != 0xFFFFFFFF) {
// SP = Target.ReadU32(VectorTableAddr);
// Target.SetReg("SP", SP);
// }
// //
// // Set up entry point PC
// //
// PC = Elf.GetEntryPointPC();
//
// if (PC != 0xFFFFFFFF) {
// Target.SetReg("PC", PC);
// } else if (VectorTableAddr != 0xFFFFFFFF) {
// PC = Target.ReadU32(VectorTableAddr + 4);
// Target.SetReg("PC", PC);
// } else {
// Util.Error("Project file error: failed to set entry point PC", 1);
// }
//}
/*********************************************************************
*
* BeforeTargetReset
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetReset (void) {
//}
/*********************************************************************
*
* AfterTargetReset
*
* Function description
* Event handler routine. Optional.
* The default implementation initializes SP and PC to reset values.
**
**********************************************************************
*/
void AfterTargetReset (void) {
_SetupTarget();
}
/*********************************************************************
*
* DebugStart
*
* Function description
* Replaces the default debug session startup routine. Optional.
*
**********************************************************************
*/
//void DebugStart (void) {
//}
/*********************************************************************
*
* TargetConnect
*
* Function description
* Replaces the default target IF connection routine. Optional.
*
**********************************************************************
*/
//void TargetConnect (void) {
//}
/*********************************************************************
*
* BeforeTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetConnect (void) {
//}
/*********************************************************************
*
* AfterTargetConnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetConnect (void) {
//}
/*********************************************************************
*
* TargetDownload
*
* Function description
* Replaces the default program download routine. Optional.
*
**********************************************************************
*/
//void TargetDownload (void) {
//}
/*********************************************************************
*
* BeforeTargetDownload
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDownload (void) {
//}
/*********************************************************************
*
* AfterTargetDownload
*
* Function description
* Event handler routine. Optional.
* The default implementation initializes SP and PC to reset values.
*
**********************************************************************
*/
void AfterTargetDownload (void) {
_SetupTarget();
}
/*********************************************************************
*
* BeforeTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetDisconnect
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetDisconnect (void) {
//}
/*********************************************************************
*
* AfterTargetHalt
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void AfterTargetHalt (void) {
//}
/*********************************************************************
*
* BeforeTargetResume
*
* Function description
* Event handler routine. Optional.
*
**********************************************************************
*/
//void BeforeTargetResume (void) {
//}
/*********************************************************************
*
* OnSnapshotLoad
*
* Function description
* Called upon loading a snapshot. Optional.
*
* Additional information
* This function is used to restore the target state in cases
* where values cannot simply be written to the target.
* Typical use: GPIO clock needs to be enabled, before
* GPIO is configured.
*
**********************************************************************
*/
//void OnSnapshotLoad (void) {
//}
/*********************************************************************
*
* OnSnapshotSave
*
* Function description
* Called upon saving a snapshot. Optional.
*
* Additional information
* This function is usually used to save values of the target
* state which can either not be trivially read,
* or need to be restored in a specific way or order.
* Typically use: Memory Mapped Registers,
* such as PLL and GPIO configuration.
*
**********************************************************************
*/
//void OnSnapshotSave (void) {
//}
/*********************************************************************
*
* OnError
*
* Function description
* Called when an error ocurred. Optional.
*
**********************************************************************
*/
//void OnError (void) {
//}
/*********************************************************************
*
* AfterProjectLoad
*
* Function description
* After Project load routine. Optional.
*
**********************************************************************
*/
//void AfterProjectLoad (void) {
//}
/*********************************************************************
*
* _SetupTarget
*
* Function description
* Setup the target.
* Called by AfterTargetReset() and AfterTargetDownload().
*
* Auto-generated function. May be overridden by Ozone.
*
**********************************************************************
*/
void _SetupTarget(void) {
unsigned int SP;
unsigned int PC;
unsigned int VectorTableAddr;
VectorTableAddr = Elf.GetBaseAddr();
//
// Set up initial stack pointer
//
SP = Target.ReadU32(VectorTableAddr);
if (SP != 0xFFFFFFFF) {
Target.SetReg("SP", SP);
}
//
// Set up entry point PC
//
PC = Elf.GetEntryPointPC();
if (PC != 0xFFFFFFFF) {
Target.SetReg("PC", PC);
} else {
Util.Error("Project script error: failed to set up entry point PC", 1);
}
}

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OpenDocument="ins_task.c", FilePath="D:/RM/@RM2025/scara_engineering/modules/imu/ins_task.c", Line=74
OpenDocument="stm32h7xx_hal_spi.c", FilePath="D:/RM/@RM2025/scara_engineering/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c", Line=3886
OpenDocument="stm32h7xx_hal_uart.c", FilePath="D:/RM/@RM2025/scara_engineering/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c", Line=3338
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SmartViewPlugin="", Page="", Toolbar="Hidden", Window="SmartView 1"
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CAD.provider=
CORTEX_M7.IPParameters=default_mode_Activation
CORTEX_M7.default_mode_Activation=1
Dma.Request0=UART5_RX
Dma.Request1=USART3_TX
Dma.Request10=USART2_TX
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Dma.Request3=USART10_RX
Dma.Request4=USART10_TX
Dma.Request5=USART1_TX
Dma.Request6=USART1_RX
Dma.Request7=UART7_RX
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Dma.Request9=USART2_RX
Dma.RequestsNb=11
Dma.UART5_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.UART5_RX.0.EventEnable=DISABLE
Dma.UART5_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART5_RX.0.Instance=DMA1_Stream0
Dma.UART5_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART5_RX.0.MemInc=DMA_MINC_ENABLE
Dma.UART5_RX.0.Mode=DMA_NORMAL
Dma.UART5_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART5_RX.0.PeriphInc=DMA_PINC_DISABLE
Dma.UART5_RX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UART5_RX.0.Priority=DMA_PRIORITY_LOW
Dma.UART5_RX.0.RequestNumber=1
Dma.UART5_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UART5_RX.0.SignalID=NONE
Dma.UART5_RX.0.SyncEnable=DISABLE
Dma.UART5_RX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UART5_RX.0.SyncRequestNumber=1
Dma.UART5_RX.0.SyncSignalID=NONE
Dma.UART7_RX.7.Direction=DMA_PERIPH_TO_MEMORY
Dma.UART7_RX.7.EventEnable=DISABLE
Dma.UART7_RX.7.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART7_RX.7.Instance=DMA1_Stream7
Dma.UART7_RX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART7_RX.7.MemInc=DMA_MINC_ENABLE
Dma.UART7_RX.7.Mode=DMA_NORMAL
Dma.UART7_RX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART7_RX.7.PeriphInc=DMA_PINC_DISABLE
Dma.UART7_RX.7.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UART7_RX.7.Priority=DMA_PRIORITY_LOW
Dma.UART7_RX.7.RequestNumber=1
Dma.UART7_RX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UART7_RX.7.SignalID=NONE
Dma.UART7_RX.7.SyncEnable=DISABLE
Dma.UART7_RX.7.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UART7_RX.7.SyncRequestNumber=1
Dma.UART7_RX.7.SyncSignalID=NONE
Dma.UART7_TX.8.Direction=DMA_MEMORY_TO_PERIPH
Dma.UART7_TX.8.EventEnable=DISABLE
Dma.UART7_TX.8.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART7_TX.8.Instance=DMA2_Stream0
Dma.UART7_TX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART7_TX.8.MemInc=DMA_MINC_ENABLE
Dma.UART7_TX.8.Mode=DMA_NORMAL
Dma.UART7_TX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART7_TX.8.PeriphInc=DMA_PINC_DISABLE
Dma.UART7_TX.8.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UART7_TX.8.Priority=DMA_PRIORITY_LOW
Dma.UART7_TX.8.RequestNumber=1
Dma.UART7_TX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UART7_TX.8.SignalID=NONE
Dma.UART7_TX.8.SyncEnable=DISABLE
Dma.UART7_TX.8.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UART7_TX.8.SyncRequestNumber=1
Dma.UART7_TX.8.SyncSignalID=NONE
Dma.USART10_RX.3.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART10_RX.3.EventEnable=DISABLE
Dma.USART10_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART10_RX.3.Instance=DMA1_Stream1
Dma.USART10_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART10_RX.3.MemInc=DMA_MINC_ENABLE
Dma.USART10_RX.3.Mode=DMA_NORMAL
Dma.USART10_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART10_RX.3.PeriphInc=DMA_PINC_DISABLE
Dma.USART10_RX.3.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART10_RX.3.Priority=DMA_PRIORITY_MEDIUM
Dma.USART10_RX.3.RequestNumber=1
Dma.USART10_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART10_RX.3.SignalID=NONE
Dma.USART10_RX.3.SyncEnable=DISABLE
Dma.USART10_RX.3.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART10_RX.3.SyncRequestNumber=1
Dma.USART10_RX.3.SyncSignalID=NONE
Dma.USART10_TX.4.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART10_TX.4.EventEnable=DISABLE
Dma.USART10_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART10_TX.4.Instance=DMA1_Stream4
Dma.USART10_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART10_TX.4.MemInc=DMA_MINC_ENABLE
Dma.USART10_TX.4.Mode=DMA_NORMAL
Dma.USART10_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART10_TX.4.PeriphInc=DMA_PINC_DISABLE
Dma.USART10_TX.4.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART10_TX.4.Priority=DMA_PRIORITY_MEDIUM
Dma.USART10_TX.4.RequestNumber=1
Dma.USART10_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART10_TX.4.SignalID=NONE
Dma.USART10_TX.4.SyncEnable=DISABLE
Dma.USART10_TX.4.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART10_TX.4.SyncRequestNumber=1
Dma.USART10_TX.4.SyncSignalID=NONE
Dma.USART1_RX.6.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.6.EventEnable=DISABLE
Dma.USART1_RX.6.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_RX.6.Instance=DMA1_Stream6
Dma.USART1_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_RX.6.MemInc=DMA_MINC_ENABLE
Dma.USART1_RX.6.Mode=DMA_NORMAL
Dma.USART1_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.6.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.6.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART1_RX.6.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.6.RequestNumber=1
Dma.USART1_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART1_RX.6.SignalID=NONE
Dma.USART1_RX.6.SyncEnable=DISABLE
Dma.USART1_RX.6.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART1_RX.6.SyncRequestNumber=1
Dma.USART1_RX.6.SyncSignalID=NONE
Dma.USART1_TX.5.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.5.EventEnable=DISABLE
Dma.USART1_TX.5.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_TX.5.Instance=DMA1_Stream5
Dma.USART1_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.5.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.5.Mode=DMA_NORMAL
Dma.USART1_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.5.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.5.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART1_TX.5.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.5.RequestNumber=1
Dma.USART1_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART1_TX.5.SignalID=NONE
Dma.USART1_TX.5.SyncEnable=DISABLE
Dma.USART1_TX.5.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART1_TX.5.SyncRequestNumber=1
Dma.USART1_TX.5.SyncSignalID=NONE
Dma.USART2_RX.9.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART2_RX.9.EventEnable=DISABLE
Dma.USART2_RX.9.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_RX.9.Instance=DMA2_Stream1
Dma.USART2_RX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART2_RX.9.MemInc=DMA_MINC_ENABLE
Dma.USART2_RX.9.Mode=DMA_NORMAL
Dma.USART2_RX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_RX.9.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_RX.9.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART2_RX.9.Priority=DMA_PRIORITY_LOW
Dma.USART2_RX.9.RequestNumber=1
Dma.USART2_RX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART2_RX.9.SignalID=NONE
Dma.USART2_RX.9.SyncEnable=DISABLE
Dma.USART2_RX.9.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART2_RX.9.SyncRequestNumber=1
Dma.USART2_RX.9.SyncSignalID=NONE
Dma.USART2_TX.10.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART2_TX.10.EventEnable=DISABLE
Dma.USART2_TX.10.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_TX.10.Instance=DMA2_Stream2
Dma.USART2_TX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART2_TX.10.MemInc=DMA_MINC_ENABLE
Dma.USART2_TX.10.Mode=DMA_NORMAL
Dma.USART2_TX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_TX.10.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_TX.10.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART2_TX.10.Priority=DMA_PRIORITY_LOW
Dma.USART2_TX.10.RequestNumber=1
Dma.USART2_TX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART2_TX.10.SignalID=NONE
Dma.USART2_TX.10.SyncEnable=DISABLE
Dma.USART2_TX.10.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART2_TX.10.SyncRequestNumber=1
Dma.USART2_TX.10.SyncSignalID=NONE
Dma.USART3_RX.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.2.EventEnable=DISABLE
Dma.USART3_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_RX.2.Instance=DMA1_Stream3
Dma.USART3_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.2.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.2.Mode=DMA_NORMAL
Dma.USART3_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.2.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART3_RX.2.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.2.RequestNumber=1
Dma.USART3_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART3_RX.2.SignalID=NONE
Dma.USART3_RX.2.SyncEnable=DISABLE
Dma.USART3_RX.2.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART3_RX.2.SyncRequestNumber=1
Dma.USART3_RX.2.SyncSignalID=NONE
Dma.USART3_TX.1.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART3_TX.1.EventEnable=DISABLE
Dma.USART3_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_TX.1.Instance=DMA1_Stream2
Dma.USART3_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_TX.1.MemInc=DMA_MINC_ENABLE
Dma.USART3_TX.1.Mode=DMA_NORMAL
Dma.USART3_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_TX.1.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_TX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART3_TX.1.Priority=DMA_PRIORITY_LOW
Dma.USART3_TX.1.RequestNumber=1
Dma.USART3_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART3_TX.1.SignalID=NONE
Dma.USART3_TX.1.SyncEnable=DISABLE
Dma.USART3_TX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART3_TX.1.SyncRequestNumber=1
Dma.USART3_TX.1.SyncSignalID=NONE
Dma.Request0=USART3_TX
Dma.Request1=USART3_RX
Dma.Request10=SPI1_RX
Dma.Request11=SPI1_TX
Dma.Request12=UART5_RX
Dma.Request2=USART10_RX
Dma.Request3=USART10_TX
Dma.Request4=USART1_TX
Dma.Request5=USART1_RX
Dma.Request6=UART7_RX
Dma.Request7=UART7_TX
Dma.Request8=USART2_RX
Dma.Request9=USART2_TX
Dma.RequestsNb=13
Dma.SPI1_RX.10.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI1_RX.10.EventEnable=DISABLE
Dma.SPI1_RX.10.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.SPI1_RX.10.Instance=DMA2_Stream3
Dma.SPI1_RX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_RX.10.MemInc=DMA_MINC_ENABLE
Dma.SPI1_RX.10.Mode=DMA_NORMAL
Dma.SPI1_RX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_RX.10.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_RX.10.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.SPI1_RX.10.Priority=DMA_PRIORITY_LOW
Dma.SPI1_RX.10.RequestNumber=1
Dma.SPI1_RX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.SPI1_RX.10.SignalID=NONE
Dma.SPI1_RX.10.SyncEnable=DISABLE
Dma.SPI1_RX.10.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.SPI1_RX.10.SyncRequestNumber=1
Dma.SPI1_RX.10.SyncSignalID=NONE
Dma.SPI1_TX.11.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI1_TX.11.EventEnable=DISABLE
Dma.SPI1_TX.11.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.SPI1_TX.11.Instance=DMA2_Stream4
Dma.SPI1_TX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_TX.11.MemInc=DMA_MINC_ENABLE
Dma.SPI1_TX.11.Mode=DMA_NORMAL
Dma.SPI1_TX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_TX.11.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_TX.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.SPI1_TX.11.Priority=DMA_PRIORITY_LOW
Dma.SPI1_TX.11.RequestNumber=1
Dma.SPI1_TX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.SPI1_TX.11.SignalID=NONE
Dma.SPI1_TX.11.SyncEnable=DISABLE
Dma.SPI1_TX.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.SPI1_TX.11.SyncRequestNumber=1
Dma.SPI1_TX.11.SyncSignalID=NONE
Dma.UART5_RX.12.Direction=DMA_PERIPH_TO_MEMORY
Dma.UART5_RX.12.EventEnable=DISABLE
Dma.UART5_RX.12.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART5_RX.12.Instance=DMA1_Stream0
Dma.UART5_RX.12.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART5_RX.12.MemInc=DMA_MINC_ENABLE
Dma.UART5_RX.12.Mode=DMA_NORMAL
Dma.UART5_RX.12.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART5_RX.12.PeriphInc=DMA_PINC_DISABLE
Dma.UART5_RX.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UART5_RX.12.Priority=DMA_PRIORITY_LOW
Dma.UART5_RX.12.RequestNumber=1
Dma.UART5_RX.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UART5_RX.12.SignalID=NONE
Dma.UART5_RX.12.SyncEnable=DISABLE
Dma.UART5_RX.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UART5_RX.12.SyncRequestNumber=1
Dma.UART5_RX.12.SyncSignalID=NONE
Dma.UART7_RX.6.Direction=DMA_PERIPH_TO_MEMORY
Dma.UART7_RX.6.EventEnable=DISABLE
Dma.UART7_RX.6.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART7_RX.6.Instance=DMA1_Stream7
Dma.UART7_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART7_RX.6.MemInc=DMA_MINC_ENABLE
Dma.UART7_RX.6.Mode=DMA_NORMAL
Dma.UART7_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART7_RX.6.PeriphInc=DMA_PINC_DISABLE
Dma.UART7_RX.6.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UART7_RX.6.Priority=DMA_PRIORITY_LOW
Dma.UART7_RX.6.RequestNumber=1
Dma.UART7_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UART7_RX.6.SignalID=NONE
Dma.UART7_RX.6.SyncEnable=DISABLE
Dma.UART7_RX.6.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UART7_RX.6.SyncRequestNumber=1
Dma.UART7_RX.6.SyncSignalID=NONE
Dma.UART7_TX.7.Direction=DMA_MEMORY_TO_PERIPH
Dma.UART7_TX.7.EventEnable=DISABLE
Dma.UART7_TX.7.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.UART7_TX.7.Instance=DMA2_Stream0
Dma.UART7_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.UART7_TX.7.MemInc=DMA_MINC_ENABLE
Dma.UART7_TX.7.Mode=DMA_NORMAL
Dma.UART7_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.UART7_TX.7.PeriphInc=DMA_PINC_DISABLE
Dma.UART7_TX.7.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.UART7_TX.7.Priority=DMA_PRIORITY_LOW
Dma.UART7_TX.7.RequestNumber=1
Dma.UART7_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.UART7_TX.7.SignalID=NONE
Dma.UART7_TX.7.SyncEnable=DISABLE
Dma.UART7_TX.7.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.UART7_TX.7.SyncRequestNumber=1
Dma.UART7_TX.7.SyncSignalID=NONE
Dma.USART10_RX.2.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART10_RX.2.EventEnable=DISABLE
Dma.USART10_RX.2.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART10_RX.2.Instance=DMA1_Stream1
Dma.USART10_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART10_RX.2.MemInc=DMA_MINC_ENABLE
Dma.USART10_RX.2.Mode=DMA_NORMAL
Dma.USART10_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART10_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART10_RX.2.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART10_RX.2.Priority=DMA_PRIORITY_MEDIUM
Dma.USART10_RX.2.RequestNumber=1
Dma.USART10_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART10_RX.2.SignalID=NONE
Dma.USART10_RX.2.SyncEnable=DISABLE
Dma.USART10_RX.2.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART10_RX.2.SyncRequestNumber=1
Dma.USART10_RX.2.SyncSignalID=NONE
Dma.USART10_TX.3.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART10_TX.3.EventEnable=DISABLE
Dma.USART10_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART10_TX.3.Instance=DMA1_Stream4
Dma.USART10_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART10_TX.3.MemInc=DMA_MINC_ENABLE
Dma.USART10_TX.3.Mode=DMA_NORMAL
Dma.USART10_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART10_TX.3.PeriphInc=DMA_PINC_DISABLE
Dma.USART10_TX.3.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART10_TX.3.Priority=DMA_PRIORITY_MEDIUM
Dma.USART10_TX.3.RequestNumber=1
Dma.USART10_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART10_TX.3.SignalID=NONE
Dma.USART10_TX.3.SyncEnable=DISABLE
Dma.USART10_TX.3.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART10_TX.3.SyncRequestNumber=1
Dma.USART10_TX.3.SyncSignalID=NONE
Dma.USART1_RX.5.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.5.EventEnable=DISABLE
Dma.USART1_RX.5.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_RX.5.Instance=DMA1_Stream6
Dma.USART1_RX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_RX.5.MemInc=DMA_MINC_ENABLE
Dma.USART1_RX.5.Mode=DMA_NORMAL
Dma.USART1_RX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_RX.5.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_RX.5.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART1_RX.5.Priority=DMA_PRIORITY_LOW
Dma.USART1_RX.5.RequestNumber=1
Dma.USART1_RX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART1_RX.5.SignalID=NONE
Dma.USART1_RX.5.SyncEnable=DISABLE
Dma.USART1_RX.5.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART1_RX.5.SyncRequestNumber=1
Dma.USART1_RX.5.SyncSignalID=NONE
Dma.USART1_TX.4.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART1_TX.4.EventEnable=DISABLE
Dma.USART1_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_TX.4.Instance=DMA1_Stream5
Dma.USART1_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART1_TX.4.MemInc=DMA_MINC_ENABLE
Dma.USART1_TX.4.Mode=DMA_NORMAL
Dma.USART1_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.4.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.4.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART1_TX.4.Priority=DMA_PRIORITY_LOW
Dma.USART1_TX.4.RequestNumber=1
Dma.USART1_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART1_TX.4.SignalID=NONE
Dma.USART1_TX.4.SyncEnable=DISABLE
Dma.USART1_TX.4.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART1_TX.4.SyncRequestNumber=1
Dma.USART1_TX.4.SyncSignalID=NONE
Dma.USART2_RX.8.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART2_RX.8.EventEnable=DISABLE
Dma.USART2_RX.8.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_RX.8.Instance=DMA2_Stream1
Dma.USART2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART2_RX.8.MemInc=DMA_MINC_ENABLE
Dma.USART2_RX.8.Mode=DMA_NORMAL
Dma.USART2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_RX.8.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_RX.8.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART2_RX.8.Priority=DMA_PRIORITY_LOW
Dma.USART2_RX.8.RequestNumber=1
Dma.USART2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART2_RX.8.SignalID=NONE
Dma.USART2_RX.8.SyncEnable=DISABLE
Dma.USART2_RX.8.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART2_RX.8.SyncRequestNumber=1
Dma.USART2_RX.8.SyncSignalID=NONE
Dma.USART2_TX.9.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART2_TX.9.EventEnable=DISABLE
Dma.USART2_TX.9.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART2_TX.9.Instance=DMA2_Stream2
Dma.USART2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART2_TX.9.MemInc=DMA_MINC_ENABLE
Dma.USART2_TX.9.Mode=DMA_NORMAL
Dma.USART2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART2_TX.9.PeriphInc=DMA_PINC_DISABLE
Dma.USART2_TX.9.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART2_TX.9.Priority=DMA_PRIORITY_LOW
Dma.USART2_TX.9.RequestNumber=1
Dma.USART2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART2_TX.9.SignalID=NONE
Dma.USART2_TX.9.SyncEnable=DISABLE
Dma.USART2_TX.9.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART2_TX.9.SyncRequestNumber=1
Dma.USART2_TX.9.SyncSignalID=NONE
Dma.USART3_RX.1.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.1.EventEnable=DISABLE
Dma.USART3_RX.1.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_RX.1.Instance=DMA1_Stream3
Dma.USART3_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.1.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.1.Mode=DMA_NORMAL
Dma.USART3_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.1.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART3_RX.1.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.1.RequestNumber=1
Dma.USART3_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART3_RX.1.SignalID=NONE
Dma.USART3_RX.1.SyncEnable=DISABLE
Dma.USART3_RX.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART3_RX.1.SyncRequestNumber=1
Dma.USART3_RX.1.SyncSignalID=NONE
Dma.USART3_TX.0.Direction=DMA_MEMORY_TO_PERIPH
Dma.USART3_TX.0.EventEnable=DISABLE
Dma.USART3_TX.0.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_TX.0.Instance=DMA1_Stream2
Dma.USART3_TX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_TX.0.MemInc=DMA_MINC_ENABLE
Dma.USART3_TX.0.Mode=DMA_NORMAL
Dma.USART3_TX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_TX.0.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_TX.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.USART3_TX.0.Priority=DMA_PRIORITY_LOW
Dma.USART3_TX.0.RequestNumber=1
Dma.USART3_TX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.USART3_TX.0.SignalID=NONE
Dma.USART3_TX.0.SyncEnable=DISABLE
Dma.USART3_TX.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
Dma.USART3_TX.0.SyncRequestNumber=1
Dma.USART3_TX.0.SyncSignalID=NONE
FDCAN1.CalculateBaudRateNominal=1000000
FDCAN1.CalculateTimeBitNominal=1000
FDCAN1.CalculateTimeQuantumNominal=25.0
@ -407,18 +445,16 @@ Mcu.Pin52=VP_TIM1_VS_ControllerModeClock
Mcu.Pin53=VP_TIM1_VS_ClockSourceITR
Mcu.Pin54=VP_TIM2_VS_ControllerModeClock
Mcu.Pin55=VP_TIM2_VS_ClockSourceITR
Mcu.Pin56=VP_TIM3_VS_ControllerModeClock
Mcu.Pin57=VP_TIM3_VS_ClockSourceITR
Mcu.Pin58=VP_TIM12_VS_ControllerModeClock
Mcu.Pin59=VP_TIM12_VS_ClockSourceITR
Mcu.Pin56=VP_TIM12_VS_ControllerModeClock
Mcu.Pin57=VP_TIM12_VS_ClockSourceITR
Mcu.Pin58=VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS
Mcu.Pin59=VP_MEMORYMAP_VS_MEMORYMAP
Mcu.Pin6=PC0
Mcu.Pin60=VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS
Mcu.Pin61=VP_MEMORYMAP_VS_MEMORYMAP
Mcu.Pin62=VP_STMicroelectronics.X-CUBE-ALGOBUILD_VS_DSPOoLibraryJjLibrary_1.4.0_1.4.0
Mcu.Pin60=VP_STMicroelectronics.X-CUBE-ALGOBUILD_VS_DSPOoLibraryJjLibrary_1.4.0_1.4.0
Mcu.Pin7=PC1
Mcu.Pin8=PC2_C
Mcu.Pin9=PC3_C
Mcu.PinsNb=63
Mcu.PinsNb=61
Mcu.ThirdParty0=STMicroelectronics.X-CUBE-ALGOBUILD.1.4.0
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
@ -437,6 +473,8 @@ NVIC.DMA1_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
NVIC.FDCAN1_IT0_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.FDCAN1_IT1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
@ -454,6 +492,7 @@ NVIC.OTG_HS_EP1_OUT_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.OTG_HS_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
NVIC.SavedPendsvIrqHandlerGenerated=true
NVIC.SavedSvcallIrqHandlerGenerated=true
@ -725,9 +764,13 @@ SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3
SH.S_TIM2_CH3.ConfNb=1
SH.S_TIM3_CH4.0=TIM3_CH4,PWM Generation4 CH4
SH.S_TIM3_CH4.ConfNb=1
SPI1.CalculateBaudRate=60.0 MBits/s
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8
SPI1.CLKPhase=SPI_PHASE_2EDGE
SPI1.CLKPolarity=SPI_POLARITY_HIGH
SPI1.CalculateBaudRate=15.0 MBits/s
SPI1.DataSize=SPI_DATASIZE_8BIT
SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,CLKPolarity,CLKPhase,BaudRatePrescaler
SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualType=VM_MASTER
SPI2.CalculateBaudRate=60.0 MBits/s
@ -748,10 +791,14 @@ TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
TIM2.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation3 CH3
TIM3.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
TIM3.IPParameters=Channel-PWM Generation4 CH4
TIM3.IPParameters=Channel-PWM Generation4 CH4,Prescaler,Period
TIM3.Period=10000-1
TIM3.Prescaler=24-1
UART5.BaudRate=100000
UART5.IPParameters=BaudRate,WordLength
UART5.WordLength=WORDLENGTH_8B
UART5.IPParameters=BaudRate,WordLength,Parity,Mode
UART5.Mode=MODE_TX_RX
UART5.Parity=PARITY_EVEN
UART5.WordLength=WORDLENGTH_9B
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
USART10.IPParameters=VirtualMode
@ -788,10 +835,6 @@ VP_TIM2_VS_ClockSourceITR.Mode=TriggerSource_ITR0
VP_TIM2_VS_ClockSourceITR.Signal=TIM2_VS_ClockSourceITR
VP_TIM2_VS_ControllerModeClock.Mode=Clock Mode
VP_TIM2_VS_ControllerModeClock.Signal=TIM2_VS_ControllerModeClock
VP_TIM3_VS_ClockSourceITR.Mode=TriggerSource_ITR0
VP_TIM3_VS_ClockSourceITR.Signal=TIM3_VS_ClockSourceITR
VP_TIM3_VS_ControllerModeClock.Mode=Clock Mode
VP_TIM3_VS_ControllerModeClock.Signal=TIM3_VS_ControllerModeClock
VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS.Mode=CDC_HS
VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_HS
board=custom